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M65818AFP
Digital Amplifier Processor of S-Master* Technology
REJ03F0019-0100Z Rev.1.00 Sep.04.2003
Description
The M65818AFP is a S-Master technique processor for digital amplifier enable to convert from multi liner-PCM digital input signal to high precise switching-pulse digital output without analog processing. The M65818AFP has built-in 24bit sampling rate converter and digital-gain-controller. The M65818AFP enables to realize high precise (Xtal oscillation precision) fully digital amplifier systems combining with power driver IC.
Features
* Built-in 24bit Sampling Rate Converter. Input Signal Sampling Rate from 32KHz to 192KHz(24bit Maximum). 4 kinds of Digital Input Format. * Built-in L/R Independent Digital Gain Control. * Built-in Soft Mute Function with Exponential Approximate-Curve. * Correspondence for SACD signal (64Fs 1bit,Fs=44.1KHz). * Direct Output from Sampling Rate Converter. * 3.3V and 5.0V Power Supply Operation at Output Clock, Input Data, and Control Signal Port
Main Applications
* Master Clock Primary Clock: 256Fsi/512Fsi Secondary Clock: 1024Fso/512Fso * Input Signal Format: MSB First Right Justified(16/20/24bit),MSB First Left Justified(24bit) LSB First Right Justified(24bit),I2S(24bit) * Input Signal Sampling Rate from 32kHz to 192kHz. * 8Fs Input Mode: Correspondence for External Digital Filter, Sampling Rate Converter Outputs. * Gain Control Function: +30dB~ -dB(0.1dB Step until -96dB, -138dB Minimum) * Third Order (16Fso:6bit/5bit,32Fso: 5bit) * Sampling Rate Converter Output :MSB First Left justified /Lch,Rch Independent/32BCK
Recommended Operating Conditions
Logic Block:3.3V10%, PWM Buffer Block : 5.0V10%
(** "S-Master" is the digital amplifier technology developed by Sony Corporation. "S-Master" is a trademark of Sony Corporation.
Rev.1.00, Sep.04.2003, page 1 of 38
M65818AFP
System Block Diagram
M65818AFP
External Input 24bit Stream Power Driver LC Filter
CD DVD Audio etc.
LRCK BCK DATA
256fsi /512fsi SACD DSD
Sampling Rate Converter 32kHz to 192kHz Clock DSD Interface
Level Control +30dB to
PWM
Stream Power Driver LC Filter
MCU I/F
Clock
1024fs/512fs
Rev.1.00, Sep.04.2003, page 2 of 38
M65818AFP
1. Pin Configuration (Top View)
(3.3V/5V System)
(3.3V System)(5V System )
P G M U T E
N S P M U T E
S C D T
S C S H I F T
S C L A T C H
MM OO DD EE 21
D V d d
M C K S E L
D V s s
X V s s
X V s s
X f s o I N
X V d d
V s s L
V s s L 1 +
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
INIT SYNC DATA BCK LRCK FsiI DSD128Fs DSD64Fs DSDR DSDL DSDCKSEL1 DSDCKSEL2 DSDCKIO TEST1 TEST2 CKCTL1 CKCTL2 BFVdd EXIOSEL EXDATAL EXDATAR EXBCK EXWCK XfsiIN
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
OUTL1+ VddL1+ VddL1OUTL1VssL1VssL2OUTL2VddL2VddL2+ OUTL2+ VssL2+ VddL VddR VssR1+ OUTR1+ VddR1+ VddR1OUTR1VssR1VssR2OUTR2VddR2VddR2+ OUTR2+
(5V System)
(5V System)
C K O U T 1
C K O U T 2
C K O U T 3
B F V s s
D V s s
T E S T 3
O F L F L A G
S F L A G
F s o C K O
F s o I
D V d d
X O V d d
XX fO sV os Os U T
V s s R
V s s R 2 +
(3.3V/5V System)
(3.3V System)(5V System)
Rev.1.00, Sep.04.2003, page 3 of 38
M65818AFP
A-1 Difference between M65818AFP and M65817AFP
M65818AFP has added the following functions to M65817AFP.
M65817AFP PWM Output Form General Pulse Width Modulation M65818AFP Selectable 4 kind of Output Form (Refer to M65818AFP Data Sheet: P28/38 System1Mode bit22,23) Selectable phase between OUTL1+/R1+ and OUTL1-/R1- to Same/Reverse (Refer to M65818AFP Data Sheet: P28/38 System1Mode bit24) Selectable operation ratio to 16fso/32fso (Refer to M65818AFP Data Sheet: P31/38 System2 Mode bit16) Selectable PWM Output Duty 50% Mute On/Off at primary side asynchronous detection (Refer to M65818AFP Data Sheet: P28/38 System1Mode bit20 ) Added the function of synchronization to primary side clock: Input the data to Sampling Rate Converter (Refer to M65818AFP Data Sheet: P28/38 System1Mode bit21)
Reverse Output Pins Function of PWM Output "OUTL1-/R1-"
Reverse Phase between OUTL1+/R1+ and OUTL1-/R1-
Operation Ratio
16fso Fixed
Selection of Muting operation at Primary Side Asynchronous Detection Selection of External 8Fs Data Input Mode
PWM Output Duty 50% Mute at primary side asynchronous detection
Only synchronize to secondary side clock (Input the data to Gain Control Block)
A-2 The Example of Evaluation Circuit
+ -
OUTL1+24 OUTL1- 21 OUTL2- 18 OUTL2+15 DATA 43 BCK 44 M65818AFP LRCK 45 10 OUTR1+ OUTR1- 7 OUTR2- 4 OUTR2+ 1
+
+
+ -
+
+
+ -
+ -
Reference Characteristics S/N THD+N 104dB(typ) 0.0014%(typ)
Condition
* * * * * * *
Input Signal : 1kHz 0dB Full scale sine wave Fs : Primary Clock 44.1kHz, Secondary Clock 48kHz PWM Output Format1 AC dithering E DC dithering 0.1% Gain Data Setting:(Index)10000b/(Mantissa)10000000b THD+N : Filter 20kHz LPF S/N : Filter 20kHz LPF + JIS-A
Rev.1.00, Sep.04.2003, page 4 of 38
M65818AFP
2. Block Diagram
E X I O S E L 59 F s i I 46 X f s i I N 64 C K SC YT NL C1 42 56 F s o C K O 73 S F L A G 72 C K C T L 2 57 M C KF Ss Eo L I 32 74 C K O U T 1 65 C K O U T 3 67 C K O U T 2 66 X f s o O U T 77 X f s o I N 28
O F L F L A G 71
EXDATAL 60
Rev.1.00, Sep.04.2003, page 5 of 38
EXDATAR 61 EXBCK 62 EXWCK63
S
P
Clock Generator (Primary) Clock Generator (Secondary)
24 21 18 15
OUTL1+ OUTL1OUTL2OUTL2+
DATA 43 BCK 44
S
P
LRCK 45
Sampling Rate Converter Gain Control
PWM
10 7 4 1
DSD128Fs 47 DSD64Fs 48
OUTR1+ OUTR1OUTR2OUTR2+
DSDR 49 DSDL 50 51 52 53 D S D C K S E L 1 D S D C K S E L 2 D S D C K I O
Down Sampling Filter
Serial Control
38 37 36 S C D T SS CC SL HA IT FC TH 35 34 M O D E 1 M O D E 2
INIT/MUTE
41 I N I T
39 40 N S P M U T E P G M U T E
54 55 T E S T 1 T E S T 2
70 T E S T 3
M65818AFP
3. Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Output Current 5V/3.3V
Name OUTR2+ VddR2+ VddR2OUTR2VssR2VssR1OUTR1VddR1VddR1+ OUTR1+ VssR1+ VddR VddL VssL2+ OUTL2+ VddL2+ VddL2OUTL2VssL2VssL1OUTL1VddL1VddL1+ OUTL1+ VssL1+ VssL XVdd XfsoIN XVss XVss DVss MCKSEL DVdd MODE1 MODE2 SCLATCH SCSHIFT SCDT NSPMUTE PGMUTE
I/O O
Description Rch PWM2(+) Output Power Supply for Rch PWM2(+) (5V) Power Supply for Rch PWM2(-) (5V) Rch PWM2 (-) Output GND for Rch PWM2(-) GND for Rch PWM1(-)
Signal Level 5V 5V 5V 5V 5V 5V 5V 5V 5V 3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V
O
O
Rch PWM1 (-) Output Power Supply for Rch PWM1(-) (5V) Power Supply for Rch PWM1(+) (5V) Rch PWM1 (+) Output GND for Rch PWM1(+) Power Supply for Rch PWM (5V) Power Supply for Lch PWM (5V) GND for Lch PWM2(+)
O
O
Lch PWM2 (+) Output Power Supply for Lch PWM2(+) (5V) Power Supply for Lch PWM2(-) (5V) Lch PWM2 (-) Output GND for Lch PWM2(-) GND for Lch PWM1(-)
O
O
Lch PWM1 (-) Output Power Supply for Lch PWM1(-) (5V) Power Supply for Lch PWM1(+) (5V) Lch PWM1 (+) Output GND for Lch PWM1(+) GND for Lch PWM
O
I
Power Supply for Master Clock Buffer Secondary Master Clock Input:1024Fso/512Fso GND for Master Clock Buffer GND for Master Clock Buffer
I
GND for Digital Block Secondary Master Clock Selection; L:1024Fso, H:512Fso Power Supply for Digital Block (3.3V) Input Mode Selection 1 Input Mode Selection 2 Serial Control*Latch Signal Input Serial Control*Shift Clock Input Serial Control*Data Input PWM Duty 50% Mute (L :Active) PWM G-MUTE (L :Active)
I I I I I I I
Rev.1.00, Sep.04.2003, page 6 of 38
M65818AFP
Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Output Current 5V/3.3V 2mA/1.5mA 2mA/1.5mA 2mA/1.5mA 2mA/1.5mA 2mA/1.5mA 2mA/1.5mA 4mA/3mA 4mA/3mA 4mA/3mA 2mA 2mA 4mA
Name INIT SYNC DATA BCK LRCK FsiI DSD128Fs DSD64Fs DSDR DSDL DSDCKSEL1 DSDCKSEL2 DSDCKIO TEST1 TEST2 CKCTL1 CKCTL2 BFVdd EXIOSEL EXDATAL EXDATAR EXBCK EXWCK XfsiIN CKOUT1 CKOUT2 CKOUT3 BFVss DVss TEST3 OFLFLAG SFLAG FsoCKO FsoI DVdd XOVdd
I/O I I I I I I I/O I/O I I I I I I I I I
Description Initialize Input(Power Supply Reset): ; L:Reset, H:Release Synchronous Set of System Clock (at Rising Edge) DATA Input (CD/MD / DVD audio mode) PCM Signal BCK Input (CD/MD / DVD audio mode) PCM Signal LRCK Input (CD/MD / DVD audio mode) PCM Signal Primary Fsi Clock Input (SACD mode) SACD Interface Clock(128Fs) SACD Interface Clock(64Fs) SACD Rch Data Input SACD Lch Data Input SACD Interface Selection 1 SACD Interface Selection 2 I/O Selection for SACD(64Fs,128Fs)Clock L:input,H:output TEST1 must be connected to GND. TEST2 must be connected to GND. fso System Clock(CKOUT1,2,3) Output Selection 1 fso System Clock(CKOUT1,2,3) Output Selection 2 Power Supply for Input/Output (3.3V/5V)Buffer 8Fs Data Input/Output Selection L:Input H:Output 8Fs Data Lch 8Fs Data Rch BCK for 8fs Data (32BCK=1WCK) Word Clock for 8fs Data (1WCK=32BCK) Primary Master Clock Input (256fsi/512fsi) fso System Clock Output 1 fso System Clock Output 2 fso System Clock Output 3 GND for Digital Block Input/Output Buffer GND for Digital Block TEST3 must be connected to GND. Overflow Detector Flag of Digital Operation (H :Active) Asynchronous Flag (H :Active) Secondary Fso Clock Output Secondary Fso Clock Input Power Supply for Digital Block(3.3V) Power Supply for Secondary Master Clock Buffer(5V)
Signal Level 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 5V/3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
I I/O I/O I/O I/O I O O O
I O O O I
Rev.1.00, Sep.04.2003, page 7 of 38
M65818AFP
Pin No. 77 78 79 80 Output Current 5V/3.3V 2mA
Name XfsoOUT XOVss VssR VssR2+
I/O O
Description Buffered Output of Secondary Master Clock (1024/512fso) GND for Secondary Master Clock Buffer GND for Rch PWM GND for Rch PWM2(+)
Signal Level 5V
4. Electrical Characteristics Absolute Maximum Ratings
Parameter Supply Voltage Symbol PWMVdd BFVdd DVdd Vi (5.0V) Vi (3.3V) Pd Tstg Min. -0.3 -0.3 -0.3 -0.3 -0.3 -40 Typ. 600 Max 6.0 6.0 4.2 Vdd+0.3V Vdd+0.3V 125 Unit V V V V V mW C Conditions 5V XVdd, XOVdd, and Vdd (PWM). 5.0V System 3.3V System
Input Voltage Range Power Dissipation Storage Temperature
Ta=60 C
Recommended Operating Conditions
Parameter Supply Voltage Symbol PWMVdd BFVdd DVdd Ta XFsoIN XFsiIN Min. 4.5 4.5 3.0 3.0 -20 16 8 Typ. 5.0 5.0 3.3 3.3 Max 5.5 5.5 3.6 3.6 75 50 25 Unit V V V V C MHz MHz Conditions 5V XVdd, XOVdd, and Vdd (PWM). 5.0V function 3.3V function
Operating Temperature Operating Frequency
Rev.1.00, Sep.04.2003, page 8 of 38
M65818AFP
DC Characteristics
(Ta=25C, PWMVdd=5V, DVdd=3.3V: Unless otherwise specified.)
Parameter H Level Input Voltage L Level Input Voltage Input Leak Current "H"Level Output Voltage Symbol VIH5 VIH3 VIL5 VIL3 Ileak VOH5 VOH3 Min. 0.75Vdd 0.75Vdd Vdd - 0.5 Vdd - 0.5 Typ. Max 0.25Vdd 0.25Vdd 10 Unit V V V V A V V Conditions BFVdd=4.5 to 5.5V BFVdd=3.0 to 3.6V BFVdd=4.5 to 5.5V BFVdd=3.0 to 3.6V BFVdd=4.5 to 5.5V IOH5=-2.0mA BFVdd=3.0 to 3.6V IOH3=-1.5mA
"L" Level Output Voltage
DSD128Fs DSD64Fs EXDATAL EXDATAR EXBCK EXWCK CKOUT1 CKOUT2 CKOUT3 XfsoOUT OFLFAG SFLAG FsoCKO OUTLXX OUTRXX DSD128Fs DSD64Fs EXDATAL EXDATAR EXBCK EXWCK CKOUT1 CKOUT2 CKOUT3
VOH5 VOH3 VOH5 VOH3
Vdd - 0.5 Vdd - 0.5 Vdd - 0.5 Vdd - 0.5

V V V V
BFVdd=4.5 to 5.5V IOH5=-4.0mA BFVdd=3.0 to 3.6V IOH3=-3.0mA BFVdd=4.5 to 5.5V IOH5=-2.0mA BFVdd=3.0 to 3.6V IOH3=-2.0mA
VOH5 VOL5 VOL3
Vdd - 0.5

0.5 0.5
V V V
VddLXX/RXX=4.5V to 5.5V IOH5=-4.0mA BFVdd=4.5 to 5.5V IOH5=2.0mA BFVdd=3.0 to 3.6V IOH3=1.5mA
VOL5 VOL3 VOL5 VOL3

0.5 0.5 0.5 0.5
V V V V
BFVdd=4.5 to 5.5V IOH5=4.0mA BFVdd=3.0 to 3.6V IOH3=3.0mA BFVdd=4.5 to 5.5V IOH5=2.0mA BFVdd=3.0 to 3.6V IOH3=2.0mA
XfsoOUT OFLFAG SFLAG FsoCKO OUTLXX OUTRXX Power Supply Current
VOL5 Idd
33
0.5
V mA
VddLXX/RXX=4.5V to 5.5V IOH5=4.0mA BFVdd=5V
5. Explanation of Operation
5.1. MODE1, MODE2 34 35
The states of MODE1 and MODE2 pins select input signal mode. MODE1 and MODE2 are control pins for input signal mode (Normal / SACD / External 8fs Input). These are selectable as follows.
Pin 34 35 Name / MODE MODE1 MODE2 Normal L L External 8fs Data L H SACD-fsi H L SACD-fso H H
Rev.1.00, Sep.04.2003, page 9 of 38
M65818AFP * Normal mode The Normal is data input mode from CD,MD,DVD etc. Input pins are DATA,BCK, and LRCK. * External 8fs Data mode In this mode, the 8fs rate data inputted from external device. Input pins are EXDATAL,EXDATAR,EXBCK and EXWCK. The data synchronized with the clock of EXBCK,EXWCK pins are inputted into EXDATAL,EXDATAR pins . Selectable "Input for primary side synchronization" and "Input for secondary side synchronization" by the serial control System1 mode bit21(EXMODE) In the case of primary side synchronization, the data inputted to the Sampling Rate Converter block. In the case of secondary side synchronization, the data inputted to Gain Control block. * SACD-fsi mode In this mode, SACD format data inputted. Input pins are DSDL,DSDR,DSD128Fs and DSD64Fs. The clock of a Down Sampling Filter is given from a *primary side, and down sampled data are inputted into the Sampling Rate Converter block. The data synchronized with the clock of DSD128Fs,DSD64Fs pins are inputted into DSDL,DSDR pins. * SACD-fso mode In this mode, SACD format data inputted. Input pins are DSDL,DSDR,DSD128Fs and DSD64Fs. The clock of a Down Sampling Filter is given from a *secondary side, and down sampled data are inputted into the Gain Control block. The data synchronized with the clock of DSD128Fs,DSD64Fs pins are inputted into DSDL,DSDR pins. * primary clock: This clock means input side clock System of the sampling rate converter. secondary clock: This clock means output side clock System of the sampling rate converter. The block after Sampling Rate Converter ( Gain Control Block, . Block, and PWM Block) operate with secondary clock "fsi", "fso", and "fs" are defined as follows in this data sheet. fsi: The primary side Sampling Frequency fso: The secondary side Sampling Frequency fs: The sampling frequency which can be set as both by the side of primary and secondary . (External 8fs Data , SACD Data etc.)
Rev.1.00, Sep.04.2003, page 10 of 38
M65818AFP 5.2. SCDT, SCSHIFT, SCLATCH 38 37 36
SCDT,SCSHIFT,and SCLATCH are input pins for setting M65818AFP's operation. Input format of SCDT, SCSHIFT and SCLATCH is shown below. * Input format of SCDT, SCSHIFT, and SCLATCH.
bit1 SCDT
24 20 15 10 5 1
SCSHIFT SCLATCH
* Mode Setting The operating Mode are classified in four and assigned by bit1and bit2. These four functions are shown below. (bit1 and bit2 ) = ( "L" and "L" ) Gain control mode: Gain control. (bit1 and bit2 ) = ( "L "and "H" ) System1 Mode: Primary block initialization, etc. (bit1 and bit2 ) = ( "H" and "L" ) System2 Mode : Secondary block initialization, etc. (bit1 and bit2 ) = ( "H" and "H" ) Test mode ( setting prohibition ) Refer to Chapter 6 about these four setting in detail. 5.3. DATA, BCK, LRCK 43 44 45
DATA, BCK and LRCK are input pins under condition of Normal mode. Input formats are supported by following 4 ways, and are set by Serial Control, "System1 Mode, bit3 and bit4". Input data length are selectable in the case of "MSB First Right Justified" (Serial Control "System1 Mode, bit5, 6"). and Input Signal Sampling Rate(1/2/4fsi) are set by Serial Control,"System1 Mode, bit7,8" Input formats are shown in following figures.
Rev.1.00, Sep.04.2003, page 11 of 38
M65818AFP * Input Formats of DATA, BCK, and LRCK
1/fsi, 1/2fsi, 1/4fsi LRCK BCK MSB DATA (24bit) 24cycle MSB first left justified(24bit) 1/fsi, 1/2fsi, 1/4fsi LRCK BCK Left Right LSB MSB 24cycle LSB Left Right
MSB DATA (16bit) MSB DATA (20bit) MSB DATA (24bit) 24 cycle 16 cycle 20 cycle
LSB
MSB
LSB
LSB
MSB
16 cycle 20 cycle
LSB
LSB
MSB
LSB 24 cycle
MSB first right justified(16bit, 20bit, 24bit) 1/fsi, 1/2fsi, 1/4fsi LRCK BCK LSB DATA (24bit) 24 cycle LSB first right justified(24bit) 1/fsi, 1/2fsi, 1/4fsi LRCK BCK 1 BCK MSB DATA (24bit) 24 cycle I2S(24bit) 1 BCK LSB MSB 24 cycle LSB Left Right MSB LSB MSB Left Right
24 cycle
5.4. EXBCK, EXWCK, EXDATAL, EXDATAR, EXIOSEL
62 63 60 61 59
When "input signal mode" is "external 8fs data mode", regardless of a setup of EXIOSEL pin, the data of 8fs rate are inputted from EXDATAL, EXDATAR pins. By setup of serial control "System1 mode:bit21", Primary Side Synchronous Input or Secondary Side Synchronous Input can be selected. In case an external 8fs data input is secondary side synchronous , the data is inputted to Gain Control Block.
Rev.1.00, Sep.04.2003, page 12 of 38
M65818AFP In case an external 8fs data input is primary side synchronous , the data is inputted to Sampling Rate Converter Block. When "input signal mode" is except a "external 8fs data mode", the output data of sampling rate converter are outputted from EXDATAL,EXDATAR pins setting up EXIOSEL pin into "H". When "input signal mode" is except a "external 8fs data mode", EXBCK, EXWCK, EXDATAL, EXDATAR pins serve as input terminals by setting up EXIOSEL pin into "L" . Therefore, when not using "external 8fs data mode", EXIOSEL can be set to "L" and other four pins (EXBCK, EXWCK, EXDATAL, EXDATAR) can be fixed to "L" or "H". EXDATAL,EXDATAR,EXBCK, and EXWCK pin's input/output format is following figure.
Input Signal Mode "External 8fs Mode" (MODE1,2=L,H) EXIOSEL pin X EXMODE Flag L H Except "External 8fs Mode" (Except MODE1,2=L,H) L H X EXWCK,EXBCK,EXDATAL,EXDATAR Input / Output Secondary Side Synchronous 8fs Data Input (24 bit effective) Primary Side Synchronous 8fs Data Input (Upper 20bit effective) Input ("L" or "H" fixed) Internal Sampling Rate Converter Output
*
EXDATAL, EXDATAR, EXBCK, and EXWCK input/output format
EXWCK 8fs EXBCK 256fs EXDATAL /EXDATAR MSB LSB
23 22 21 20
987
1
0
MSB first left justified (24bit)
5.5. DSDL, DSDR, DSD128Fs, DSD64Fs, DSDCKSEL1, DSDCKSEL2, DSDCKIO 50 49 47 48 51 52 53 When "input signal mode" is "SACD-fsi Mode" or "SACD-fso Mode", the data is inputted to DSDL,DSDR pins. Under SACD-fsi mode, the clock of a Down Sampling Filter is given from a primary side, and down sampled data are inputted into the Sampling Rate Converter block. Under SACD-fso mode, the clock of a Down Sampling Filter is given from a *secondary side, and down sampled data a inputted into the Gain Control block. The states of DSDCKSEL1,DSDCKDEL2 pins select 4 "SACD timing mode". DSDCKIO pin select input or output pin-type of DSD128Fs/DSD64Fs clock for data fetch. The relations of DSDCKSEL1 and DSDCKSEL2 pins and SACD input format mode setting are following figures.
DSDCKSEL1 L L H H DSDCKSEL2 L H L H SACD timing mode mode1 mode2 mode3 mode4
Rev.1.00, Sep.04.2003, page 13 of 38
M65818AFP Setting of DSDCKIO is following table.
DSDCKIO L H Selection of DSD64fs and DSD128fs I/O Input mode Output mode
* SACD Input Format
mode1 DSDL/R (input data) DSD128fs DSD64fs mode2 DSDL/R (input data) DSD128fs DSD64fs 128fs 64fs 128fs 64fs XD0 D1
D0
XD1 D2 XD2
D3
XD3
D0 XD0
D1
XD1
D2
XD2 D3
XD3
mode3 DSDL/R (input data) 128fs DSD128fs 64fs DSD64fs mode4 DSDL/R (input data) DSD128fs DSD64fs 64fs
D0
XD0 D1
XD1 D2 XD2
D3
XD3
D0
D1
D2
D3
* D0:Positive phase data, XD0:Negative phase data (reversal) Positive phase data are fetched at the timing of "O" marks in upper figure.
5.6. MCKCEL, XfsoIN, XfsoOUT XfsoIN pin is secondary master clock input.
32 28 77
The state of MCKSEL pin selects secondary master clock.
MCKSEL L H XfsoIN 1024fso 512fso
XfsoOUT pin is buffered-output from XfsoIN pin's input clock.
Rev.1.00, Sep.04.2003, page 14 of 38
M65818AFP 5.7. XfsiIN XfsiIN pin is primary master clock input. Frequency of primary master clock must be selected by the serial control "System2 mode:bit3".
bit3(IMCKSEL) H L XfsiIN 512fsi 256fsi
64
* The relations between input signal sampling rate and master clock frequency.
Input sampling rate 1fsi: 32k / 2fsi: 64k / 4fsi: 128k 1fsi: 44.1k / 2fsi: 88.2k / 4fsi: 176.4k 1fsi: 48k / 2fsi: 96k / 4fsi: 192k Primary clock 512fsi/256fsi[Hz] 16.384M/8.192M 22.579M/11.290M 24.576M/12.288M Secondary clock 1024fso/512fso[Hz] 32.768M/16.384M 49.152M/24.576M
Input signal and primary clock are related to synchronization. The primary clock frequency are 512 or 256 times as much as the input signal fsi ( 32k, 44.1k and 48k.) The primary and secondary clock are related to independence. ( asynchronization ) At 1024fso setting, secondary clock= frequency range from 32.768MHz to 49.152MHz. At 512fso setting, secondary clock = frequency range from 16.384MHz to 24.576MHz. 5.8. CKCTL1, CKCTL2, CKOUT1, CKOUT2, CKOUT3 56 57 65 66 67
CKOUT1, CKOUT2, and CKOUT3 pins are divided-clock output from secondary clock. At power on, these frequency is free-running. The states of CKCTL1 and CKCTL2 pins selects clock frequency of CKOUT1,CKOUT2,and CKOUT3 pins. The setting table of CKCTL1 and CKCTL2 pins is shown below.
CKCTL1 L L H H CKCTL2 L H L H CKOUT1 L 256Fso 512Fso 512Fso CKOUT2 L 16Fso 256Fso 256Fso CKOUT3 L 8Fso 16Fso 8Fso
5.9. FsoCKO
73
FsoCKO is clock output pin of 1fso frequency. The output is divided-clock of XfsoIN, and frequency is free-running at power on. FsoCKO pin's clock is utilized for a synchronization in case that have used plural M65818AFP,take a synchronization between M65818AFP and other external devices. Detail explanation is shown in next paragraph, "SYNC". 5.10. SYNC, FsoI, FsiI, SFLAG 42 74 46 72
M65818AFP synchronizes in clock input from the external source devices. So it makes synchronized operation between source devices or another M65818AFP ( in case of Multi channel Operation ) The clock which can be set as the object of an synchronization is a clock of FsoI (1fso), FsiI (1fsi), LRCK (1/2/4 fsi), and EXWCK (8fs). The object clock changes by input signal mode setting. These relations are shown in following table.
Rev.1.00, Sep.04.2003, page 15 of 38
M65818AFP M65818AFP detects rise edge of these synchronized clock in normal operation, and the M65818AFP does operation of resynchronization in case that the cycle has changed. In addition, the M65818AFP re-synchronizes for a synchronized clock, in case that M65818AFP detects SYNC pin's rises edge, too. This SYNC function exists also in serial control "System2 mode:bit6" under the same name. While re-synchronizing, SFLAG pin outputs "H" and data is muted inside.
Synchronization detection clock Input Signal Mode Normal External 8fs Data SACD-fsi SACD-fso * Internal 8 dividing clock Primary Side Synchronization Secondary Side Synchronization FsiI Primary Side LRCK EXWCK * Secondary Side FsoI FsoI FsoI FsoI FsoI
In the case of using Multiplex(for multi channel application) and Single (for 2ch application) , detail explanation is shown according to each "signal input mode" below. * Normal Mode The primary side: It synchronizes with LRCK. All ICs synchronize with an input device by connecting common LRCK. The Secondary side: It synchronizes with FsoCKO of Master IC. One of M65818AFP becomes a master IC, and the synchronization between ICs is carried out by FsoCKO of Master IC. FsoCKO pin outputted from this master IC is entered each FsoI pins of master and slave ICs. The primary side: It synchronizes with LRCK. Therefore M65818AFP synchronizes with source devices. The secondary side: there is no need for external devices and other ICs to synchronize, therefore FsoCKO is connected to FsoI, In other way, By setting secondary side asynchronous detection to "disable" with "ASYNCEN2" flag(Serial Control,System2 mode,bit8), FsoI can also be considered as fixation. In this mode, M65818AFP always perform synchronous detection between LRCK pin's clock in primary side. Therefore with regardless to a setup by the serial control "System1 mode:bit16(ASYNCEN1)", the synchronous detection perform as forced-enable. * External 8fs Data Mode (The case of primary side synchronization) The primary side: M65818AFP synchronizes with EXWCK (internal 8 dividing clock). All ICs synchronize with an input device by connecting common EXWCK. The secondary side: M65818AFP synchronizes with FsoCKO of Master IC. One of M65818AFP becomes a master IC, and the synchronization between ICs is carried out by FsoCKO of Master IC. FsoCKO pin outputted from this master IC is entered each FsoI pins of master and slave ICs.
Rev.1.00, Sep.04.2003, page 16 of 38
M65818AFP The primary side: M65818AFP synchronizes with EXWCK (internal 8 dividing clock). Thereby it synchronize with an input device. The secondary side: there is no need for external devices and other ICs to synchronize, therefore FsoCKO is connected to FsoI, In other way, By setting secondary side asynchronous detection to "disable" with "ASYNCEN2" flag(Serial Control,System2 mode,bit8), FsoI can also be considered as fixation. In this mode, M65818AFP always perform synchronous detection between EXWCK pin's clock in primary side. Therefore with regardless to a setup by the serial control "System1 mode:bit16(ASYNCEN1)", the synchronous detection perform as forced-enable. * External 8fs Data Mode (The case of secondary side synchronization) (common) The primary side: Synchronous operation does not carry out since internal sampling rate converter is not used. In this mode, asynchronous detection by the primary side is set to disable by force. Therefore with regardless to a setup by the serial control "System1 mode:bit16(ASYNCEN1)", the synchronous detection perform as forced-disable. The Secondary Side: M65818AFP synchronizes with FsoCKO of Master IC (in single use, it is own IC). One of the M65818AFP becomes a master, and the synchronization between ICs is carried out by FsoCKO of Master IC.FsoCKO pin outputted from this master IC is entered each FsoI pins of master and slave ICs. Moreover, the rise edge of FsoCKO sent from M65818AFP and the rise edge of EXWCK (8fs) which comes from the external device need to be with a synchronous phase. * SACD-fsi Mode The primary side: M65818AFP synchronizes with FsiI inputted in common to each IC. And primary side synchronous DSD128Fs/DSD64Fs are used as a clock in common to all ICs. Thus, DSD128 Fs/DSD64Fs in common to all ICs is inputted (all IC DSDCKIO=L) or the DSD128 Fs/DSD64Fs output (DSDCKIO="H") generated by dividing of the primary side master clock within Master IC is inputted Into the DSD128 Fs/DSD64Fs (DSDCKIO="L") of other slaves IC. The synchronous operation of the SACD input in the case of multi is possible by doing in this way. The secondary side: M65818AFP synchronizes with FsoCKO of Master IC. One of M65818AFP becomes a master IC, and the synchronization between ICs is carried out by FsoCKO of Master IC. FsoCKO pin outputted from this master IC is entered each FsoI pins of master and slave ICs. The primary side: Input to FsiI pin or set FsiI as fixed by setting primary side asynchronous detection to disable by serial control "System1 mode:bit16 (ASYNCEN1)". The secondary side: there is no need for external devices and other ICs to synchronize, therefore FsoCKO is connected to FsoI, In other way, By setting secondary side asynchronous detection to "disable" with "ASYNCEN2" flag(Serial Control,System2 mode,bit8), FsoI can also be considered as fixation.
Rev.1.00, Sep.04.2003, page 17 of 38
M65818AFP * SACD-fso Mode The primary side: Synchronous operation does not carry out since internal sampling rate converter is not used. In this mode, asynchronous detection by the primary side is set to disable by force. Therefore with regardless to a setup by the serial control "System1 mode:bit16(ASYNCEN1)", the synchronous detection perform as forced-disable. The secondary side: M65818AFP synchronizes with FsoCKO of Master IC. One of M65818AFP becomes a master IC, and the synchronization between ICs is carried out by FsoCKO of Master IC. FsoCKO pin outputted from this master IC is entered each FsoI pins of master and slave ICs. And DSD128Fs/DSD64Fs for secondary synchronization are connected as a clock in common to all ICs. Thus, DSD128 Fs/DSD64Fs in common to all ICs is inputted (all IC DSDCKIO="L") or the DSD128 Fs/DSD64Fs output (DSDCKIO="H") generated by dividing of the primary side master clock within Master IC is inputted into the DSD128 Fs/DSD64Fs (DSDCKIO="L") of other slaves IC. The synchronous operation of the SACD input in the case of multi is possible by doing in this way. The primary side: Synchronous operation does not carry out since internal sampling rate converter is not used. In this mode, asynchronous detection by the primary side is set to disable by force. Therefore with regardless to a setup by the serial control "System1 mode:bit16(ASYNCEN1)", the synchronous detection perform as forced-disable. The secondary side: there is no need for external devices and other ICs to synchronize, therefore FsoCKO is connected to FsoI, In other way, By setting secondary side asynchronous detection to "disable" with "ASYNCEN2" flag(Serial Control,System2 mode,bit8), FsoI can also be considered as fixation.
Rev.1.00, Sep.04.2003, page 18 of 38
M65818AFP The examples of a connection diagram The case of the multi use (6ch) in each input mode are shown in the following figure.
Normal Mode
LRCK (Primary) ASYNCEN1=don't care ASYNCEN2=enable Master FsoCKO (Secondary) LRCK FsiI FsoI EXWCK
Slave
LRCK FsoI FsiI EXWCK
Slave
LRCK FsoI FsiI EXWCK
External 8fs Data Mode
(The Case of Primary Side Synchronization)
ASYNCEN1=don't care ASYNCEN2=enable Master FsoCKO (Secondary) LRCK EXWCK (Primary) FsiI FsoI EXWCK
External 8fs Data Mode (The case of secondary side synchronization)
ASYNCEN1=don't care ASYNCEN2=enable
Master
LRCK FsiI FsoI EXWCK
EXWCK (Secondary) FsoCKO (Secondary)
Slave
LRCK FsoI FsiI EXWCK
Slave
LRCK FsoI FsiI EXWCK
Slave
LRCK FsiI FsoI EXWCK
Slave
LRCK FsiI FsoI EXWCK
SACD-fsi Mode
ASYNCEN1=enableMaster : DSDCKIO=L DSD128Fs/64Fs ASYNCEN2=enableSlave : DSDCKIO=L (Primary) Master FsoCKO LRCK (Secondary) FsiI (Primary) FsiI FsoI EXWCK DSD128Fs/64Fs (Primary) ASYNCEN1=enable Master : DSDCKIO=H ASYNCEN2=enable Slave : DSDCKIO=L
Master
LRCK FsiI FsoI EXWCK
FsiI (Primary)
FsoCKO (Secondary)
Slave
LRCK FsiI EXWCK FsoI
Slave
LRCK FsoI FsiI EXWCK
Slave
LRCK FsoI FsiI EXWCK
Slave
LRCK FsoI FsiI EXWCK
SACD-fso Mode
ASYNCEN1=don't care Master : DSDCKIO=L ASYNCEN2=enable Slave : DSDCKIO=L ASYNCEN1=don't care Master : DSDCKIO=H ASYNCEN2=enable Slave : DSDCKIO=L
Master
LRCK FsiI FsoI EXWCK DSD128Fs/64Fs (Secondary)
Master
LRCK FsiI FsoI EXWCK DSD128Fs/64Fs (Secondary)
Slave
LRCK FsoI FsiI EXWCK
Slave
LRCK FsoI FsiI EXWCK
Slave
LRCK FsoI FsiI EXWCK
Slave
LRCK FsoI FsiI EXWCK
Rev.1.00, Sep.04.2003, page 19 of 38
M65818AFP The examples of a connection diagram The case of the single use (2ch) in each input mode are shown in the following figure.
Normal Mode
ASYNCEN1=don't care ASYNCEN2=enable FsoCKO LRCK FsiI FsoI EXWCK ASYNCEN1=don't care ASYNCEN2=disable LRCK (Primary) LRCK FsoI FsiI EXWCK
LRCK (Primary)
External 8fs Data Mode (The Case of Primary Side Synchronization)
ASYNCEN1=don't care ASYNCEN2=enable FsoCKO LRCK EXWCK (Primary) FsiI FsoI EXWCK EXWCK (Primary) ASYNCEN1=don't care ASYNCEN2=disable LRCK FsoI FsiI EXWCK
External 8fs Data Mode (The case of secondary side synchronization)
ASYNCEN1=don't care ASYNCEN2=enable LRCK FsiI FsoI EXWCK EXWCK (Secondary) FsoCKO (Secondary)
SACD-fsi Mode
DSDCKIO=L ASYNCEN1=enable ASYNCEN2=enable LRCK FsoI FsiI EXWCK FsoCKO DSDCKIO=H ASYNCEN1=disable ASYNCEN2=disable LRCK FsoI FsiI EXWCK
DSD128Fs/64Fs (Primary) FsiI (Primary)
DSD128Fs/64Fs (Primary)
SACD-fso Mode
DSDCKIO=L ASYNCEN1=don't care ASYNCEN2=enable LRCK FsoI FsiI EXWCK FsoCKO DSD128Fs/64Fs (Secondary) DSDCKIO=H ASYNCEN1=don't care ASYNCEN2=disable LRCK FsoI FsiI EXWCK
DSD128Fs/64Fs (Secondary)
Rev.1.00, Sep.04.2003, page 20 of 38
M65818AFP 5.11. OFLFLAG 71
OFLFLAG pin is output the 'over flow flag' in the operation. OFLFLAG pin outputs "H" level by detection of over flow from Gain Control Block and others. The "H" level width is over 0.6msec, so detection result is held. 5.12. OUTL1+, OUTL1-, OUTL2+, OUTL2-, OUTR1+, OUTR1-, OUTR2+, OUTR2OUTL1+, OUTL1-, OUTL2+, OUTL2-, OUTR1+, OUTR1-, OUTR2+, and OUTR2- pins are pulse output modulated output signal to PWM signal. These pins are connected to external Power Driver ICs.
PWM Output Form 1, 2, 3 and 4 can be selected by serial control data(System1 mode:bit22,23 ). PWM Output Form1 : General Modulation PWM Output Form2 : Symmetrical Modulation PWM Output Form3 : Modulation returned with time domain. (The rise and fall edge of Lch and Rch in a term are reverse.) PWM Output Form4: Modulation returned with time domain. (The rise and fall edge of Lch and Rch in a term are same timing.) In each 4 forms, the operating rate and bit length of PWM Output can be changed following the setting of And the output mute function and the output pins reverse function, can be controlled by the pin setting or serial control. The PWM output control is shown in the following table.
Item Output Form Operation Output Form Selection 1,2,3,4 Select to 16fso/6bit ,16fso/5bit ,32fso/5bit from operating rate and data bit length of Setting Operation Set up by the serial control system 1 mode bit 22,23 (PWM MODE 0 and 1). (Refer to Chapter 6.2. system 1 mode for details) Set up by the serial control system 2 mode bit16 and bit17. (Refer to Chapter 6.3. system 2 mode for details.)
Operating Rate and Data Bit Length
.
PWM operation are synchronized by this setting. Output Muting Duty 50% Mute Set NSPMUTE pin "L" or set up by serial control System 2 mode bit14 (NSPMUTE) "H". (Refer to Chapter 5.13.NSPMUTE pin description and 6.3.system2 mode for details) Set PGMUTE pin "L" or set up by serial control system2 mode bit15(PGMUTE) "H". (Refer to Chapter 5.14.PGMUTE pin description and 6.3 system2 mode for details) Set up by serial control system2 mode bit9 (CHSEL ). Set up by serial control system1 mode bit124(PWMHP). (Refer to Chapter 6.2. system1 mode for details.)
Absolute Zero Mute
Reverse Output Pins Function
Reverse on Lch and Rch of output pins. Reverse for OUTL1- and OUTR1- of output pins.( Output OUTL1+ /R1+ data to OUTL1- /OUTR1data.)
Rev.1.00, Sep.04.2003, page 21 of 38
M65818AFP 5.13. NSPMUTE 39
NSPMUTE pin is input to make for PWM output to 50% duty mute. "L": PWM output 50% duty Mute. '"H": Mute release.
5-14. PGMUTE
40
PGMUTE pin is input to make PWM output to absolute zero mute. "L": PWM output mute. The case of System1 mode:bit24,PWMHP = "L" OUTL1 (+), OUTL2 (+), OUTR1 (+), OUTR2 (+) : "L" fixed OUTL1 (-), OUTL2 (-), OUTR1 (-), OUTR2 (-) : "H" fixed The case of System1 mode:bit24,PWMHP = "H" OUTL1 (+), OUTL2 (+), OUTR1 (+), OUTR2 (+) ,OUTL1(-),OUTR1(-) : "L" fixed OUTL2 (-), OUTR2 (-) : "H" fixed "H": MUTE release. 5.15 INIT INIT is the pin for reset to all functions of M65818AFP. "L" level : (1). Clear of data memory. (2). Initialization of Serial Control. (3). PWM output Duty 50 %. "L" period needs more than 5 msec. "H" level : usual operation. "L">"H" rise edge: Resynchronization treatment, which is same at SYNC function. 41
5.16. TEST1, TEST2, TEST3 TEST1,TEST2, and TEST3 pins are test input for factory shipping test of M65818AFP. TEST1,TEST2, and TEST3 pins must be tied to "L" level on usual operation. 5.17. Power Supply and GND Power supply and GND routes have 5 isolated lines. (1)VddL1+, VssL1+, VddL1-, VssL1-, VddL2+, VssL2+, VddL2-, VssL2-, VddR1+, VssR1+, VddR1-, VssR1-, VddR2+, VssR2+, VddR2-, VssR2-, VssL, VddL, VssR, VddR These pins are Power supply and GND for PWM output buffer block. It has a pair of independent Power Supply, and GND to each 8 output pin. Power Supply voltage must be fixed at 5.0V. (2)XVdd, XVss 27 29 30 These pins are Power supply and GND for XfsoIN clock input block. Power Supply voltage must be fixed at 5.0V. (3)XOVdd, XOVss 76 78 These pins are Power supply and GND for XfsoOUT clock output block. Power Supply voltage must be fixed at 5.0V. (4)DVdd, DVss 75 69 These pins are Power supply and GND for digital block and fixed input/output buffer only for 3.3V (32,70-74 pins). Power Supply voltage must be fixed at 3.3V
Rev.1.00, Sep.04.2003, page 22 of 38
M65818AFP (5)BFVdd, BFVss 58 68 These pins are Power supply and GND for input/output buffer (3.3V/5V ). In a case that BFVdd pin is applied at 5.0V, input/output voltage level of 34-67pins becomes 5.0V signal level. In another case that BFVdd pin is supplied at 3.3V, input/output pins (34-67 pins) becomes 3.3V signal level. 5.18. Power sequences System power-on sequencing * Refer to following figure.
System power-on sequencing
Power( Vddxxx,XVdd, XOVdd, DVdd, BFVdd)
Power OFF Power ON
* Refer to following figure.
Master clock ( XfsoIN, XfsiIN) INIT
X X X X X
Over 5msec(*1)
SCDT SCSHIFT SCLATCH
Over 0sec(*2)
Over 2/fso(*3)
*1 After a power supply and Master clock become to stable, INIT pin must be "L" over 5 msec. *2 Data transfer is possible right after INIT release. *3 Until SCLATCH is operated, a period over 2/fso ( fso=48kHz, over 42usec ) is necessary after INIT release.
Rev.1.00, Sep.04.2003, page 23 of 38
M65818AFP
6. Serial Control
6.1. Gain Control Mode No setting bits means "Don't care".
bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 GAIN0 GAIN1 GAIN2 GAIN3 GAIN4 GAIN5 GAIN6 GAIN7 GAIN8 GAIN9 GAIN10 GAIN11 GAIN12 Gain Data Index (MSB) Gain Data Index Gain Data Index Gain Data Index Gain Data Index (LSB) Gain Data Mantissa (MSB) Gain Data Mantissa Gain Data Mantissa Gain Data Mantissa Gain Data Mantissa Gain Data Mantissa Gain Data Mantissa Gain Data Mantissa (LSB) Flag Name MODE1 MODE2 TEST1 TEST2 NSLMT1 NSLMT2 GCONT1 GCONT2 Functional Explanation Mode Setting 1 Mode Setting 2 Test Mode 1 Test Mode 2 Output Limit 1 Output Limit 1 Channel selection for Gain Control Block 1 Channel selection for Gain Control Block 2 Refer to Table 6-1-2. L / R independence Lch L/R common Rch H L "L" fixed "L" fixed "L" fixed "L" fixed INIT L L L L L L H L L L L H L L L L L L L
* Output Limit (bit5,bit6:NSLMT1 ,NSLMT2 ) The M65818AFP has Over Flow Limit function which detects by input signal level and limit gain control. Limit value is set by Gain Control Mode :bit5,bit6 "NSLMT1, NSLMT2" and System2 Mode:bit17"NSOBIT". The limit value setting of Gain control block and PWM output. Table (6-1-1a). Limit Value [In the case of 6bit mode, System2 mode:bit17(NSOBIT)="L"]
DSLMT1 L H L H DSLMT2 L L H H Gain Block 0.9375 0.90625 0.875 0.84375 PWM Output (Limit Value from DS Block ) 63 values (31) 61 values (30) 59 values (29) 57 values (28)
Rev.1.00, Sep.04.2003, page 24 of 38
M65818AFP Table (6-1-1b). Limit Value [In the case of 5bit mode System2 mode:bit17(NSOBIT)="H"]
DSLMT1 L H L H DSLMT2 L L H H Limit Value of Gain 0.90625 0.875 0.84375 0.8125 PWM Output Value (Limit Value from Block) 31 values (15) 31 values (15) 29 values (14) 29 values (14)
* Channel Selection for Gain Control Block (bit7,bit8:GCONT1 ,GCONT2 ) These bit selection enable to control gain data "L/R common" or "L/R independence". GCONT1 :"L"...L/Rch common, "H"...L/Rch independence. GCONT2 :"L"...Rch only, "H"...Lch only. Bit8 is available only the case of bit7 = "H". * The index and Mantissa part of Gain Data. (bit12 -bit24,: GAIN0 -GAIN12 ) The Gain value is set from bit12 to bit24. Index part: bit12 (MSB) to bit16(LSB) Mantissa part: bit17 (MSB) to bit24 (LSB) The Gain Data is assigned 13bits, composed of Index part 5bits and of Mantissa part 8bits, The range of Index parts is following statements. Index part: 10100b(16.0) to 10000b(1.0) to 00000b( 2 ) The range of mantissa part is following as statement. Index part; 10100b to 00001b: Mantissa part; 11111111b to 10000000b (128 step/1 Index). Index part;00000b: Mantissa part; 11111111b to00000000b (256 step). Initial value: Index part: 10000b Mantissa part:10000000b infinity zero: Index part: 00000b Mantissa part:00000000b # Notice of GAIN value Setting continuously In the case of GAIN value Setting continuously, for example of Setting L/Rch independently, please take the interval time (pulse interval time of SCLATCH signal) more than 1/fso.For example, in the case of fso=48kHz, please take the interval time more than 21sec. * The Gain Data and Audio Output Level. Gain data consists of 13bits (Index part; 5bit, Mantissa part; 8bit ). e.g. 10000b(1.0)/10000000b(0.5) means 0.5(0dB).
-16
Rev.1.00, Sep.04.2003, page 25 of 38
M65818AFP Table (6-1-2). The Gain Data and Output Level
Gain Data 10100/11111111 (b) to 10001/10000000 (b) to 10000/10000000 (b) 01111/11111111 (b) to 00000/10000000 (b) to 00000/00000001 (b) 00000/00000000 (b) Polarity + Absolute Output Value 15.9375 to 1.0 to 0.5 0.498046875 to -16 0.5* to 0.00390625*2-16 infinity zero Output Level +30.069dB to +6.021dB to 0dB -0.0340dB to -96.330dB to -138.474dB -
* Calculation method of Gain value. The way to calculation of Gain value from Gain Data is following equation.
Gain value = 20log [ 2

X
Mantissa data (decimal value) 128
]
dB
* Soft Mute. The Soft Mute function is executed by setting of Gain Data as 00000/00000000b ( "/" :means dividing point between index part and mantissa part). The release from Soft Mute function must be executed by setting the gain data before soft mute. The Soft Mute function and release from there don't have linear curve but have characteristics of approximate exponential curve.
Output amplitude
16
0.5
T = xxxx/Fs(sec)
0 T
00000/00000000b
t
\
T
10000/10000000b setting
Rev.1.00, Sep.04.2003, page 26 of 38
M65818AFP * Operating time of Soft Mute Total steps from Maximum value(10100b/11111111b) to Minimum value(00000b/00000000b) (128steps/1 index) x (20index (10100b-10000b)) +256steps = 2816steps. The transition term of up and down depend on 2fso clock. Therefore, in case of fso=48kHz, T=1/2fso=10.416sec/step, transition term are following. From Maximum value (10100b/11111111b) to Minimum value (00000b/00000000b) : 2816T=29.333msec. From 0dB value (10000b/10000000b) to Minimum value (00000b/0000000b) : 2304T=24msec 6dB transition term (when over 00000b/10000000b (=-96dB) value ) : 128T=1.333msec. * Soft Attenuate. Transition from older Gain Attenuation to newer Gain Attenuation always operates with Soft Mute function. For example, in case of Gain1 > Gain3 > Gain2, transition process is shown below. At first, GAIN1 is operated, then second, GAIN2 is operated. In case that GAIN2 is operated faster than GAIN1 of transition completion (refer to "A" situation in figure) GAIN1 is ignored and data approaches at GAIN2. Further, GAIN3 is operated faster than GAIN2 of transition completion( Refer to "B" or "C" situation in figure), GAIN2 is ignored and data approaches at GAIN3.
Gain
1.0 A (GAIN1) B 0 C -1.0 (GAIN2) (GAIN3)
t
Rev.1.00, Sep.04.2003, page 27 of 38
M65818AFP 6.2. System1 Mode
bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ASYNC1MODE EXMODE PWMMODE0 PWMMODE1 PWMHP Select process under asynchronization in primary side Mode select of external 8fs data input Selection of Output PWM Form Reverse Phase of OUTL1-/R1ASYNCEN1 synchronous Detection Flag for Primary Side Flag Name MODE1 MODE2 IFMT0 IFMT1 IBIT0 IBIT1 ISF0 ISF1 EMPFS1 EMPFS2 DF1IMUTE DF2IMUTE Zero Mute of DATA input Zero Mute at sampling rate converter input Active Active don't care don't care don't care enable don't care don't care don't care Zero Mute Sync. by primary side Refer to Table 6-2-5 Active PWM:duty 50% Sync. by secondary side L L L Non-active L L disable Non-active Non-active Functional Explanation Mode Setting 1 Mode Setting 2 Input Format Selection Setting for Input Word Length Input Sampling Rate Selection Fs selection for De-emphasis Filter H "H" fixed Refer to Table 6-2-1. Refer to Table 6-2-2. Refer to Table 6-2-3. Refer to Table 6-2-4. L "L" fixed INIT L L L L L L L L L L
Table 6-2-1 Input Format
bit 3 4 Flag Name IFMT0 IFMT1 MSB First Left Justified L L MSB First Right Justified H L LSB First Right Justified L H IS H H
2
Table 6-2-2 Setting for Input Data Word Length
bit 5 6 Flag Name IBIT0 IBIT1 16bit L L 20bit H L 24bit L H Don't use H H
Table 6-2-3 Input Sampling Rate Selection (fsi: 32k to 48kHz 2fsi: 64k to 96kHz, 4fsi: 128k to 192kHz)
bit 7 8 Flag Name ISF0 ISF1 fsi L L 2fsi H L 4fsi L H Don't use H H
Rev.1.00, Sep.04.2003, page 28 of 38
M65818AFP Table 6-2-4 Fs Selection for De-emphasis filter (De-emphasis is "ON" except for bit9=L and bit10=L)
bit 9 10 Flag Name EMPFS1 EMPFS2 32.0K H H 44.1K L H 48.0K H L OFF L L
Table 6-2-5 Selection of PWM Output form
bit 22 23 Flag Name PWMMODE0 PWMMODE1 PWM Output Form L L PWM Output Form H L PWM Output Form L H PWM Output Form H H
*Output Form 2 is available only under following conditions. MCKSEL="L" (Secondary Side Master Clock 1024fso) , Serial Control System2 mode, bit17( NSOBIT) = "H" (5bit), bit16( NSSPEED) = "L" (16fso). In case of the setting and release for PWM Output Form 2, Refer to "The NOTE1 at setting PWM output Form 2" on next page. * Selection of Input format (bit3,bit4:IFMT0,IFMT1) Selection of Input format function is available only condition of Normal mode. Refer to Table 6-2-1
Otherwise, Selection of Input format function is unavailable under conditions of External 8fs Input and SACD Input modes (Interlocked with MODE1 and MODE2 pins). Detail setting of External 8fs Input and SACD modes are shown in Chapter 5-4 and 5-5. * Setting of Input Word Length (bit5,bit6:IBIT0,IBIT1). 2. Setting of Input Data Word Length is available only MSB First Right Justified. * Selection of Input Sampling Rate (bit7,bit8:ISF0,ISF1). 3. * Fs Selection for De-emphasis Filter on/off (bit9, bit10 : EMPFS1, EMPFS2). 4. (bit9,bit10): ("L","L")... De-emphasis Filter is "off". except ("L","L")... De-emphasis Filter on (Fs setting). * Zero Mute at data input (bit11: DF1IMUTE). DF1IMUTE : "L"...Mute release. "H"...Mute. The input data from DATA pin under normal mode is muted in this setting. * Zero Mute at Sampling Rate Converter Input (bi12: DF2IMUTE). DF2IMUTE : "L"...Mute release. "H"...Mute. DF2IMUTE is available for sampling rate converter input data. DF2IMUTE executes zero mute of input data from DATA pin under condition of Normal mode and from DSDL/DSDR pins under condition of SACD-fsi mode.
Rev.1.00, Sep.04.2003, page 29 of 38
Refer to Table 6-2-
Refer to Table 6-2-
Refer to Table 6-2-
M65818AFP
* "Enable" of Primary Side Asynchronous Detection Flag (bi16: ASYNCEN1). Bit16 controls "enable"/"disable" of primary-side-asynchronous-detection-circuit. ASYNCEN1 : "L"...disable. "H"...enable. Under condition of ASYNCEN1 ="L", primary side asynchronous detection is unavailable whether the clock is not inputted to FsiI pin, thereby M65818AFP does not operate function under asynchronization, for instance mute operation. However, Primary Side Asynchronous Detection is available only condition of SACD-Fsi mode. * Selection of Muting operation at primary Side Asynchronous Detection (bit20:ASYNC1MODE) "L" ...Duty 50% Mute of PWM output at primary side asynchronous detection. "H"... Input Zero Mute of the gain control at primary side asynchronous detection. (PWM Output 50% Mute doesn't be operated in this setting.) * Selection of Data Input Mode for external 8fs.(bit21: EXMODE) "L"...A setup in case an external 8fs data input is secondary side synchronous. (Data is inputted to Gain Control Block) "H"...A setup in case an external 8fs data input is primary side synchronous. (Data is inputted to Sampling Rate Converter Block) * Selection of PWM output form (bit22, 23:PWMMODE 0 and 1) 5. The selection of PWM output form 1, 2, 3, and 4 , refer to Chapter 5-12 for the details. *NOTE1 : At the setting of PWM Output Form2 PWM Output Form2 enable to operate the following conditions. bit17 NSOBIT) "H" (5bit), bit16(NSSPEED)="L"(16 fso) Only in terminal MCKSEL="L" (secondary side master clock 1024 fso) In the case of setting and release for PWM Output Form2, set both flags as follows. * Serial Control System1 Mode, bit 22, 23 (PWMMODE0,1 ) * Serial Control System2 Mode: bit16 (NSSPEED), bit17 (NSOBIT) (1) Set to Serial Control System2 mode : bit17(NSOBIT)="H" bit16(NSSPEED )="L". (To be set as MCKSEL="L" in advance is required.) (2) Serial control System1 mode:bit22, 23(PWMMODE0,1)="H","L" When a setup of both (1) and (2) is completed, it changes to Form2. When (2) is set up before (1), The term until a setup of (1) holds the last PWM Output Form. (1) Serial control System1 mode:bit22, bit 23 (PWMMODE 0 , 1) is set as the Form to be used. (2) Serial Control System2 mode:bit17(NSOBIT),bit16(NSSPEED) is set the condition to be used. When a setup of (1) is completed, PWM Output Form changes. When (2) is set up before (1), a term until a setup of (1) is worked keeps the Form 2 in the state of serial control System2 mode:bit17(NSOBIT) ="H", bit16(NSSPEED) ="L". Refer to Table 6-2-
Rev.1.00, Sep.04.2003, page 30 of 38
M65818AFP *NOTE2; Selection of PWM output form Pay attention in selection and setting above-mentioned that a noise may occur by internal clock changes when setting of MCKSEL pin is changed and the serial control System2 mode: bit17 (NSOBIT) and bit16 (NSSPEED). Since especially MCKSEL pin sets up an internal master clock, use with a fixed value recommended. In changing MCKSEL, initialization with INIT pin and a re-setup of all the bits by serial control are needed after changing MCKCEL. * Reverse Phase of PWM Output OUTL1(-) / OUTR1(-) (bit24:PWMHP) "L"...PWM Output OUTL1(-) / OUTR1(-) are reverse phase as the PWM output OUTL1(+) / OUTR1(+) . "H"...PWM Output OUTL1(-) / OUTR1(-) are same phase as the PWM output OUTL1(+) / OUTR1(+) . In this mode, the signal which added OUTL1(-) / OUTR1(-) and OUTL2(-) / R2(-) by external resistance can be given to LPF / Headphone Amplifier.
6.3. System2 Mode (Secondary side)
bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Flag Name MODE1 MODE2 IMCKSEL DSDFCO0 DSDFCO1 SYNC XFsoOEN ASYNCEN2 CHSEL DRPOL SRCRST Functional Explanation Mode Setting 1 Mode Setting 2 Input Master Clock Selection Filter Coefficient of Down Sampling Resynchronization XfsoOUT pin output "enable"
Asynchronous Detection Flag for secondary Side
H "H" fixed 512fsi Refer to Table 6-3-1. L->H : Resynchronization. disable enable Active Negative-phase Active don't care Active Active Active 32fso 5 bits (31 value) Negative-phase Refer to Table 6-3-2 Negative-phase Refer to Table 6-3-3
L "L" fixed 256fsi
INIT L L L L
enable disable Non-active Positive-phase Non-active
L L L L L L L L L L L L
L / R inversion of PWM output
Block: Rch Input Phase
Sampling Rate Converter Reset Zero Mute at Gain Control Input Clock Duty 50 percent Mute of PWM Output G_MUTE of PWM Output Data
GIMUTE NSPMUTE PGMUTE NSSPEED NSOBIT DCDRPOL DCDSEL0 DSDSEL1 ACDRPOL ACDSEL0 ACDSEL1 ACDSEL2
Non-active Non-active Non-active 16fso 6 bits (63 value) Positive-phase
Block: Operation Speed Block: Setting of Output
Bit Number Block: Rch Phase of DC dithering Block: DC dithering Selection
Block: Rch Phase of AC
dithering Block: AC dithering selection
Positive-phase
L L L L L
Rev.1.00, Sep.04.2003, page 31 of 38
M65818AFP Table 6-3-1 Setting of Down Sampling Filter Coefficient
bit 4 5 Flag Name DSDFCO0 DSDFCO1 ROM1 L L ROM2 H L ROM3 L H ROM4 H H
Table 6-3-2 DC dithering Selection at Block
bit 19 20 Flag Name DCDSEL0 DCDSEL1 Non-dithering L L DC dithering 0.1% H L DC dithering 0.2% L H DC dithering0.4% H H
Table 6-3-3 AC dithering Selection at Block
bit 22 23 24 Flag Name ACDSEL0 ACDSEL1 ACDSEL2 Non-dithering don't care L L AC dithering A L H L AC dithering C L L H AC dithering E L H H
Table 6-3-4 Setup Operating Rate & Bit Length of Block
bit 16 17 pin Flag / Pin Name NSSPEED NSOBIT MCKSEL 16fso,6bit L L L(Secondary Clock1024fso) 16fso,5bit L H L(Secondary Clock1024fso) 16fso,5bit X X L(Secondary Clock512fso) 32fso,5bit H H L(Secondary Clock1024fso)
* Input Master Clock Selection (bit3:IMCKSEL). "L":256fsi "H":512fsi ("512fsi" are divided into half "256fsi" and operate as primary master clock.) * Selection of Down Sampling Filter Coefficient for SACD input (bi4, bit5: DSFCO 0,DSFCO 1). Refer to Table 6-3-1. * Resynchronization (bit6: SYNC). Resynchronization function is same at SYNC pin's function. Refer to Operation Explanation, Chapter 5.10. Resynchronization process starts by SYNC rise edge, therefore SYNC level must be fixed to "L" just before SYNC operation. * "Enable" of XfsoOUT pin Output(bit7: XfsoOEN). "L": Clock Output (enable), "H": L fixed (disable) * Flag to "Enable" Asynchronous Detection for Secondary Block (bit8: ASYNCEN2). ASYNCEN2 : "L"...disable. "H"...enable. Under condition of ASYNCEN2="L", secondary side asynchronous detection is in-effective under asynchronous position, whether Fsol Clock is not inputted, there by M65818AFP does not operate function for instance mute operation.
Rev.1.00, Sep.04.2003, page 32 of 38
M65818AFP * Reverse Lch/Rch for PWM Output pins(bit9: CHSEL). "L": Lch/Rch no reverse, "H": Lch/Rch reverse. * : Rch Input Phase (bit10: DRPOL). "L".... Same phase ("Through") "H".....This setting makes Rch Input in reverse, further makes PWM block input phase reverse, ultimately phase becomes positive phase ( Input pin and Output pin's phase is same). * Sampling Rate Converter Block Reset (Initialize function) (bit11: SRCRST). "L" .....normal operation "H" to "L" edge.....Reset ( Initialize function) * Zero Mute of Gain Control Input (bit13: GIMUTE). "L"...Mute release, "H"...Mute. * Duty 50% Mute of PWM Output (bit14: NSPMUTE). Fixed PWM duty 50% Mute "L".....Mute release "H"..... Mute This function exists also in a pin by the same name.(This Mute function can be set either NSPMUTE flag or NSPMUTE pin.) * G-Mute for PWM Output Data (bit15: PGMUTE) At G-MUTE flag = H , PGMUTE pin fixes each PWM Output as followings. "L"..... Mute release "H"..... Fixed Mute for PWM Output (Fixed value as follows) OUTL1(+) and OUTR1(+) ="L" , OUTL2(+) and OUTR2(+) = "L" OUTL1(-) and OUTR1(-) ="H" , OUTL2(-) and OUTR2(-) = "H" OUTL1(+) and OUTR1(+) ="L" , OUTL2(+) and OUTR2(+) = "L" OUTL1(-) and OUTR1(-) ="L" , OUTL2(-) and OUTR2(-) = "H" This function exists also in a pin by the same name.(This Mute function can be set either PGMUTE flag or PGMUTE pin.)
* Block : operating rate (bit16: NSSPEED).
Refer to Table 6-3-4.
"L"...16fso "H"...32fso *Enable only MCKSEL="L"(1024fso), NSOBIT="H" only. (Except for this condition, Operating rate automatically becomes 16fso.)
* Block : The setting of bit length (bit17: NSOBIT).
Refer to Table 6-3-4.
NSOBIT selects bit length for operation. This is set by force as 5bit at MCKSEL="H". "L"...6bit (63 value) "H"...5bit (31value) * Block: DC dithering Rch Phase (bit18: DCDRPOL). "L"...Same phase "H"...Reverse phase
* Block: DC dithering Selection (bit19,bit20: DCDSEL0,DCDSEL1).
Refer to Table 6-3-2.
Rev.1.00, Sep.04.2003, page 33 of 38
M65818AFP * Block: AC dithering Rch Phase (bit21: ACDRPOL). "L"...Same phase "H"...Reverse phase * Block: AC dithering Selection (bit22,bit23,bit24: ACDSEL0,ACDSEL1,ACDSEL2). Refer to Table 6-3-3.
7.1. AC Characteristics Lists. (Ta=25 C, PWM Vdd=5V, DVdd=3.3V)
AC Characteristics Parameter XfsoIN duty ratio XfsiIN duty ratio SCSHIFT pulse time SCDT setup time SCDT hold time SCLATCH pulse width SCLATCH setup time SCLATCH hold time BCK pulse width DATA setup time DATA hold time LRCK setup time LRCK hold time EXBCK pulse time EXWCK setup time EXWCK hold time EXDATA L / R setup time EXDATA L / R hold time EXDATA L / R output delay time EXWCK output delay time DSD128fs pulse width DSD64fs pulse width DSD64fs setup time DSD64fs hold time DSD L / R setup time DSD L / R hold time SYNC pulse width Symbol duty(XfsoIN) duty(XfsiIN) tw(SCSHIFT) tsu(SCDT) th(SCDT) tw(SCLATCH) tsu(SCLATCH) th(SCLATCH) tw(BCK) tsu(DATA) th(DATA) tsu(LRCK) th(LRCK) tw(EXBCK) tsu(EXWCK) th(EXWCK) tsu(EXDATA) th(EXDATA) tpd(EXDATA) tpd(EXWCK) tw(DSDCK128) tw(DSDCK64) tsu(DSDCK64) th(DSDCK64) tsu(DATA) th(DATA) tw(SYNC) Output load capacity 10 [pF] Output load capacity 10 [pF] 70 mode 1, 3 mode 1, 3 mode 1, 2, 3, and 4 mode 1, 2, 3, and 4 140 40 40 40 40 160 512fsi 256fsi Conditions Min. 40 30 40 160 80 80 160 160 160 35 20 20 20 20 35 20 20 20 20 1.0 1.0 Typ. 50 50 50 Max. 60 70 60 Units % % nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec
Rev.1.00, Sep.04.2003, page 34 of 38
M65818AFP 7.2. AC Characteristics Timing Chart (1) XfsoIN, XfsiIN Duty Ratio
twhl twh twl duty (XfsoIN,XfiIN) =
(2) SCSHIFT, SCDT, SCLATCH input timing Chart
twh twhl
tw(SCSHIFT) SCSHIFT tsu(SCDT) SCDT SCLATCH
tw(SCSHIFT)
th(SCDT)
) tw(SCLATCH ) th(SCLATCH tsu(SCLATCH )
(3) BCK, DATA, and LRCK Input timing Chart
tw(BCK) BCK
tw(BCK)
tsu(DATA) DATA
th(DATA) th(LRCK) tsu(LRCK)
LRCK
(4) EXBCK, EXDATAL, EXDATAR, EXWCK input timing Chart
tw(EXBCK) EXBCK
tw(EXBCK)
tsu(EXDATA) EXDATAL EXDATAR EXWCK
th(EXDATA) th(EXWCK)
tsu(EXWCK)
(5) EXBCK, EXDATAL, EXDATAR, EXWCK output timing Chart
tw(EXBCK) EXBCK EXDATAL EXDATAR EXWCK
tw(EXBCK)
tpd(EXDATA) tpd(EXWCK)
Rev.1.00, Sep.04.2003, page 35 of 38
M65818AFP (6) DSD64Fs, DSD128Fs, DSDL, DSDR Input Timing Chart
mode1
tw(DSDCK128) tw(DSDCK128)
DSD128Fs DSD64Fs DSDL DSDR
tsu(DSDCK64) tsu(DATA)
tw(DSDCK64) th(DSDCK64) th(DATA)
tw(DSDCK64)
mode2
tw(DSDCK64) tw(DSDCK64)
DSD64Fs
tsu(DATA) th(DATA)
DSDL DSDR
mode3
tw(DSDCK128) tw(DSDCK128)
DSD128FS
tw(DSDCK64) tsu(DSDCK64) th(DSDCK64) th(DATA)
tw(DSDCK64)
DSD64Fs
tsu(DATA)
DSDL DSDR
mode4
tw(DSDCK64) tw(DSDCK64)
DSD64Fs
tsu(DATA) th(DATA)
DSDL DSDR
Rev.1.00, Sep.04.2003, page 36 of 38
M65818AFP
8. Application Example
External 8fs Data Input: External Sampling Rate Converter Output: External DAC
External 8FsData Input/Output Setting L: Input H: Output
DSP
E X D A T A (Primary Side Clock)L
LRCK BCK DATA XfsiIN
E X D A T A R
E X B C K
E X W C K
E X I O S E L
MCKSEL XFsoIN
(Secondary Side Clock)
Set Secondary Clock L:1024Fso H:512Fso
Oscillator
SACD Decoder
DSD128FS DSD64Fs DSDR DSDL FsiI
(Clock for a primary side synchronization)
XFsoOUT OUTL1+ OUTL1OUTL2+ OUTL2-
Secondary Clock Output
Power Driver
Set Timing 1 SACD Interface Set Timing 2 SACD Interface
DSDCKSEL1 DSDCKSEL2 DSDCKIO
Select shift clock I/O for DSD L: Input H: Output
M65818AFP
OUTR1+ OUTR1OUTR2+ OUTR2-
Power Driver
MCU
Initialize Mute Input Re-Synchronization
Set Input Mode1 Set Input Mode 2
SCDT SCSHIFT SCLATCH INIT PGMUTE NSPMUTE SYNC MODE1 MODE2
T E S T 1 T E S T 2 T E S T 3 O F L F L A G S F L A G
FsoCKO FsoI
Clock for a secondary side synchronization (for Multi channel use)
CKCTL1 CKCTL2 CKOUT1 CKOUT2 CKOUT3
Set Secondary Clock 1 Set Secondary Clock 2
Secondary Clock Output 1 Secondary Clock Output 2 Secondary Clock Output 3
Flag Output
Rev.1.00, Sep.04.2003, page 37 of 38
M65818AFP
80P6N-A
JEDEC Code -- MD
e
MMP
Weight(g) 1.58 Lead Material Alloy 42
Plastic 80pin 1420mm body QFP
Package Dimensions
EIAJ Package Code QFP80-P-1420-0.80 HD D
65 64
E
24 41
25
40
HE
A2
c
x
M
A1
Rev.1.00, Sep.04.2003, page 38 of 38
1
b2
I2 Recommended Mount Pad Symbol
A L1
A A1 A2 b c D E e HD HE L L1 x y L
Detail F
F e
b
y
b2 I2 MD ME
Dimension in Millimeters Min Nom Max -- -- 3.05 0.1 0.2 0 2.8 -- -- 0.3 0.35 0.45 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.8 -- -- 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 -- -- -- -- 0.2 0.1 -- -- 0 10 -- 0.5 -- -- 1.3 -- -- 14.6 -- -- -- -- 20.6
ME
80
Sales Strategic Planning Div.
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