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(e3505) M43C505
MARC4 - 4-bit Microcontroller for LCD Applications
The M43C505 (e3505) is a member of the MARC4 family of low cost, single chip CMOS microcontrollers. This 4-bit C contains an on-chip RC oscillator, CPU core, RAM, ROM, I/O, 32-kHz crystal oscillator, 15-stage prescaler/interval timer and liquid crystal display driver circuitry.
Features
Benefits
D D D D D D
4 bit stack oriented Harvard architecture 4 K x 8 bit application ROM 253 x 4 bit of on-chip RAM 13 bidirectional I/O lines 4 input lines with interrupt facility Fast on-chip RC oscillator core operating frequency min. 1 MHz at 3 Volts (2 ms instruction cycle time)
D Built-in LCD voltage generation with temperature
compensation (constant contrast)
D SLEEP mode for battery-operated applications D RAM and core register contents valid at VDD = 2.0 V (C in SLEEP mode; Tamb = 0 ...+75 _C) D Independent power supplies (C-crystal oscillator) D High level language qFORTH with a highly optimizing compiler
D Separate watch crystal oscillator for time keeping D 2 external and 2 interval timer / prescaler interrupts D Master reset and static power-on reset circuitry with
brown-out function
D Piggyback version for program evaluation D Metal-ROM version M45C535 (e3535) for fast prototyping (see Appendix)
D Programmable LCD module for up to 80 segment
D PC based development system
TST1 TST2
TCL
NRST
VDD
VSS
System clock generation
Sleep
Power-on reset
ROM 4096 x 8 bit Program counter Instruction bus Interrupt controller
RAM address registers X Y SP RP Memory bus Instruction decoder I/O bus CCR TOS
RAM 253 x 4 bit
ALU
I/O
I/O + strobe 32 kHz LCD driver
C1 C2 VEE2 VEE1 VREG
4
4
Inputs key int. 4
I/O 4
External interrupts
Oscillator Prescaler
PORT 1 PORT 0 PORT 5 OD
PORT 4 INT7
AVDD COM0...3 AVSS INT2, S01...20 BUZZER 32 kHz
96 12020
Figure 1. Block diagram of M43C505
Rev. A3, 13-Jan-99
1 (40)
M43C505 (e3505)
64 S17 S18 S19 S20 BP40 BP41 BP42 BP43 n.c. VSS TCL TST1 TST2 1 S16 S15 S14 S13 S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01 COM3 COM2 COM1 19 20 COM0 VEE1 C1 C2 VEE2 VREG INT7 VDD INT2 IP53 IP52 IP51 IP50 32 52 51
M43C505 M45C535
OSCIN n.c. n.c. n.c. AVDD AVSS OSCOUT NRST BP10 BP11 BP12 BP13 BP00 BP01 OD NST n.c. BP02 BP03
33
96 12021
Figure 2. M43C505/ M45C535 in 64-pin plastic QFP (top view) Table 1. Pin description
AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA
Power supply voltage +2.4 V to 6.2 V Analogue power supply voltage +2.4 V to 6.2 V Circuit ground Analogue circuit ground Regulated, temperature compensated supply voltage for 5 V LCD panels Storage capacitor pin for doubled LCD voltage Storage capacitor pin for tripled LCD voltage Pump capacitor connection pins for LCD 4 bidirectional I/O lines of Port 0 - automatic nibblewise configurable I/O 4 bidirectional I/O lines of Port 1 - automatic nibblewise configurable I/O Output strobe during read access from Port 0 (see figure 6) Output strobe during write access to Port 0 (see figure 6) 4 bidirectional I/O lines of Port 4 (*) - automatic nibblewise configurable I/O 4 input lines of Port 5 with interrupt facility (*) LCD backplane driver outputs LCD segment driver outputs External interrupt input pin (*) External interrupt input or buzzer output pin (*) Test mode inputs, used to control different test modes (internal pull-up) Clock input/output for system clock (during test mode) 32-kHz quartz crystal connection pins Reset input, a logic low on this pin resets the device (*) For mask options, please see the ordering information. 2 (40) Rev. A3, 13-Jan-99
Name VDD AVDD VSS AVSS VREG VEE1 VEE2 C1, C2 BP00 - BP03 BP10 - BP13 OD NST BP40 - BP43 IP50 - IP53 COM0-COM3 S01-S20 INT7 INT2/BUZ TST1, TST2 TCL OSCIN;OSCOUT NRST
Function
(e3505) M43C505
Contents
1 Signal Description, I/O Programming, Memory, Core Registers, and Self-Check . . . . . . . . . . . . . 1.1 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 VDD, VSS, AVDD and AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.2 VREG, VEE1, VEE2, C1 and C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.3 NRST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.4 TCL (RC Oscillator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.5 TST1, TST2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.6 OSCIN, OSCOUT (Crystal Oscillator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.7 I/O Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.8 BP00-BP03, NST and OD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.9 BP10-BP13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.10 BP40-BP43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.11 IP50-IP53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.12 COM0-COM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.13 S01-S20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.14 INT2, INT7 (External Interrupts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.15 Buzzer (INT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 Bidirectional Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 Input Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Core Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.1 Accumulator (TOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 Expression Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 RAM Address Register (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.4 Return Stack Pointer (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.6 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.7 Self-Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Modes, Interrupts, and Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Reset Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 External Reset (NRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.3 Effects on Internal Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 7 7 7 7 8 9 10 10 10 10 10 10 10 11 12 12 12 12 12 12 13 14 14 14 15
2
Rev. A3, 13-Jan-99
3 (40)
M43C505 (e3505)
Contents (continued)
2.4 2.5 Interval Timer/Prescaler Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 Prescaler during SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 17 17 18 19 19 20 20 20 20 21 21 22 24 26 28 28 28 29 30 31 31 34 34 35 35 38 38 39 40
3
Liquid Crystal Display Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Display Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 LCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Initializing the LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 LCD Driver - Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 LCD Voltage and Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Maximum LCD Drive Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Direct Drive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 2:1 Multiplex Drive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 3:1 Multiplex Drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 4:1 Multiplex Drive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 DC Operating Characteristics, VDD = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 DC Operating Characteristics, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 DC Operating Characteristics, VDD = 2.4 to 5.5 V, Tamb = +25_C . . . . . . . . . . . . . . . . . . . . . . 4.5 DC Electrical Characteristics, VDD = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 DC Electrical Characteristics, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Emulation Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Pad Coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix M45C535 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Pad Coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5
6
7
4 (40)
Rev. A3, 13-Jan-99
(e3505) M43C505
1 Signal Description, I/O Programming, Memory, Core Registers, and Self-Check
1.1.4 TCL (RC Oscillator)
The system clock for the C is derived from a fully integrated on-chip RC oscillator circuit. This oscillator tracks the supply and temperature to ensure optimum operation of the microcontroller under all conditions (see figures 29 and 30). The TCL pin can be used as clock input for an external CMOS oscillator. In this configuration the low power SLEEP mode cannot be used and care must be taken with the reset conditions. The TCL pin must be held low for at least 1ms after the release of power-on or an external reset to allow the external clocking mode.
This section provides a description of the I/O signals, the input/output programming, memory, core registers, and a description of the self-check.
1.1
1.1.1
Signal Description
VDD, VSS, AVDD and AVSS
Power is supplied to the microcontroller using these pins. VDD is power for the C core, RAM, ROM and the peripherals, VSS is ground. AVDD is power for the crystal oscillator and AVSS is ground.
1.1.2
VREG, VEE1, VEE2, C1 and C2
VREG is the temperature compensated reference for the LCD voltage booster circuitry. It is used for building up the doubled (VEE1) and tripled (VEE2) voltage levels required by multiplexed LCDs. The pump capacitor for the voltage generator is connected between C1 and C2. Storage capacitors must be attached at VEE1 and VEE2 towards VSS (see figure 16). As mask programmable option VREG can be either supplied from an external source or generated internally.
1.1.5
TST1, TST2
These two lines contain integrated pull-up transistors and define different production and emulation test modes. When both are high, the C is in the normal operation mode.
1.1.6
OSCIN, OSCOUT (Crystal Oscillator)
1.1.3
NRST
The NRST input is not required for startup but can be used to reset the internal state of the microcontroller and provide an orderly software startup procedure. Refer to Reset modes in section 2 for a detailed description.
Normally a 32-kHz standard watch crystal is connected to these pins. As mask programmable option a built-in capacitor of 20 pF can be connected to each pin. To ensure proper operation of the crystal oscillator a chosen crystal should follow the specification given in the table below.
C1 R S B
(a)
32.768 kHz
*) Customer Option
(b) A
L
OSCIN 20 pF * Rp R
OSCOUT 20 pF *
C0 A B
96 12022
Figure 3. (a) Crystal oscillator - (b) equivalent circuit Table 1. Standard crystal specification
Parameter Frequency Series resistance Static/Shunt capacitance Dynamic capacitance Load capacitance
Symbol f RS C0 C1 CL
Typ. 32.768 30 1.5 3 10
Max. 100 50
12.5
Unit kHz k pF fF pF
Rev. A3, 13-Jan-99
5 (40)
M43C505 (e3505)
The crystal and components should be mounted as close as possible to the input pins to minimize output distortion and startup stabilization time. Use of an external CMOS oscillator is recommended when crystals outside of the above specified range are to be used. M43C505
OSCIN OSCOUT
N.C. External clock
Figure 4. External clocking
96 12023
1.1.7
I/O Address Map
Table 2. Port address map
Port 0 1 2 3 4 5 6 15
Direction I/O I/O Output Output I/O Input Output Output
Function Bidirectional port with two strobe lines (NST, OD) Bidirectional port LCD control port (see table 6) LCD data port Bidirectional port (with open drain output as mask option) Input port with interrupt facility Interrupt mask/buzzer output control register (see table 4) Prescaler/interval timer control port (see table 5) programming paragraph for more details concerning the programming.
Table 2 contains the port address and a short functional description of the on-chip modules.
1.1.8
BP00-BP03, NST and OD
1.1.11
IP50-IP53
These four I/O lines and two strobe output lines (NST, OD) comprise Port 0. The port consists of CMOS output drivers with an integrated pull-up resistor in the input mode. The direction of the port is software programmable and all Port 0 lines are configured as input during power-on or external reset. Refer to the Input/Output programming paragraph for a more detailed description.
1.1.9
BP10-BP13
These four input lines comprise Port 5. As a mask programmable option each input line can be used with or without an integrated pull-up resistor. The Port 5 logic is capable of generating an additional interrupt (priority level 4), when any of the four input lines is driven low. This function is disabled after power-on or external reset. Refer to the Input/Output programming paragraph for more details concerning the programming.
These four I/O lines comprise Port 1. The port contains CMOS output drivers with an integrated pull-up resistor in the input mode. The direction of the port is software programmable and all Port 1 lines are configured as input during power-on or external reset. Refer to the Input/ Output programming paragraph for a more detailed description.
1.1.12
COM0-COM3
1.1.10
BP40-BP43
These four output lines provide the backplane drive signals which should be connected directly to the liquid crystal display unit. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required the unused outputs should not be connected.
These four I/O lines comprise Port 4. As mask programmable option each I/O line can be used as CMOS or open drain output and with or without an integrated pull-up resistor in the input mode. See figure 5 in the following paragraph for a port schematic diagram. The direction of the complete port is software programmable and all Port 4 lines are configured as input during power-on or external reset. Refer to the Input/Output
1.1.13
S01-S20
These 20 segment output lines provide the segment drive signals which should be connected directly to the liquid crystal display unit. The segment output signals are generated in accordance with the multiplexed backplane signals and with the data resident in the display latch. When less than 20 segment outputs are required the unused segment outputs should not be connected.
6 (40)
Rev. A3, 13-Jan-99
(e3505) M43C505
1.1.14 INT2, INT7 (External Interrupts)
1.2
1.2.1
Input/Output Programming
Bidirectional Ports
The external interrupt inputs are negative edge triggered and have Schmitt-trigger characteristics to improve the noise immunity. The microcontroller completes the current instruction before it responds to the interrupt request. When the interrupt input pin is driven low a logic one is latched internally to signify the interrupt request, if the corresponding enable bit in the mask register is set. When the microcontroller completes its current instruction, the interrupt pending register is tested. If an interrupt is pending and the interrupt enable bit in the condition code register is set, the interrupt sequence begins. See Interrupts in section 2 for more details.
1.1.15
Buzzer (INT2)
The INT2 pin is bidirectional. When set to input, this pad functions as an external, maskable interrupt. When set to output the programmer can choose between a static output value or an audio frequency square wave. The buzzer frequency of 2.048 or 4.096 kHz is selectable as a mask programmable option. See Interrupts in section 2 for more details on programming.
Port 0, 1, and 4 may be programmed as an input or an output under software control. The direction of a port is determined by an IN or OUT instruction and is held until another IN or OUT instruction for this port is executed. The direction of these bidirectional ports is not switchable on a bit wise basis. The output latches hold the state of the last data value written to the port. At power-on or external reset all pins of Port 0, 1, and 4 are set to input mode and all output latches are set to a logic 1. Whenever the port is switched from input to output the last value stored in the latches will appear on the outputs for one clock cycle (see figure 6). When switching bidirectional ports from output to input the stray capacitance of the connection wires may cause the data read to be the same as the last data written to this port. This behaviour can be used by connecting large enough capacitors to the pins of the bidirectional port to read back the previous data written to this port. On the other hand, to avoid the negative effects of stray capacitances one of the following approaches should be used: D Use two IN instructions, and DROP the first data nibble read. D Write Fh to the port to be read before executing the IN instruction.
VDD
* Customer Options (for Port 4 only)
*
*
I/O Ctrl D R POR I/O Bus D S
Q NQ
Port_Dir
ESD Protection
BPxy
Q
Data Out
Data In
96 12024
Figure 5. Bidirectional port schematics
Rev. A3, 13-Jan-99
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M43C505 (e3505)
Bidirectional Port 0 The bidirectional Port 0 supports a hardware interface for external devices which require a data write strobe and a data read strobe pin. The NST pin is an active low strobe issued when data written to Port 0 is valid. The OD signal is a strobe indicating that data is being read from Port 0 by the C. Data must be valid at the latest 100 ns after the falling edge of OD (figure 6).
TCL
Instr.
Port0
IN
OR
Port0
OUT
LIT_2
Port0
Fh
Data
Hi-Z (internal pull-up)
***
Data valid
Port_Dir0
Output mode
Input mode
Output mode
NST
OD
*** Last written data contained in output latches, Fh after power-on-reset
96 12025
Figure 6. Read and write cycle timing at Port 0 (OD, NST)
1.2.2
Input Port 5
* Customer Option VDD *
The data on Port 5 is sent to the top of the expression stack whenever an IN instruction (addressing Port 5) is executed. The Port 5 logic may generate an additional interrupt (priority level 4), when any of the four input lines is driven low. This function is useful for implementing an interrupt driven keyboard. It is disabled after power-on or external reset. The corresponding interrupt level 4 is enabled by writing any value to Port 5 and automatically disabled after a read operation from Port 5. The interrupt service routine may use the prescaler to perform a software based keypad debouncing.
I/O bus 0
ESD Protection
IP50
INT4 Enable
IP51 IP52 IP53
96 12026
Figure 7. Port 5 with pull-up option
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1.3 Memory
special subroutines accessible with single byte (SCALL) instructions. The corresponding memory map is shown in figure 8. The self test routines should be included as part of the free program space. The 16-bit check sum (CRC) is located by the compiler in the last two bytes of ROM. The on-chip 256 x 4 bit RAM is divided in the 12-bit wide return stack, the 4-bit wide expression stack (both with a user definable depth) and the data memory. The fixed return address (000h) which points to the $AUTOSLEEP routine is located at RAM address FCh. The MARC4 family of microcontrollers is based on the Harvard architecture with physically separate program memory (ROM) and data memory (RAM). The program memory (ROM) is mask programmed with the customer application program during the fabrication of the microcontroller. The ROM is addressed by a 12-bit wide program counter, thus limiting the program size to a maximum of 4096 bytes which cannot be extended by using external memory. The user ROM starts with a 512 byte segment ("Zero Page") which contains predefined start addresses for interrupt service routines and
ROM
(4K x 8 bit)
RAM
(256 x 4 bit) Auto-Sleep Zero Page FCh 000h Y 0 0 0
000h 1FFh Zero Page Self tests (200 bytes) $RESET free program space $AUTOSLEEP
008h
Global Variables
X INT1 INT2 INT3 INT4 INT5 INT6 080h 0C0h 100h 140h 180h 1C0h 1E0h 00h 4 x 4 bit
Figure 8. Memory map
96 11560
SP
(TOS-1)
RP
FFEh FFFh
16 bit ROM check sum
INT7
Rev. A3, 13-Jan-99
CC CCCCCC C CCCC C CCCC CCCCCC CCC CCCC CCC C CCC CCCCCC CCCCC CC C CCCC CCC
S0
INT0
040h
unused
Expression Stack
Return Stack
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1.4 Core Registers
PC
As shown in the programming model, the MARC4 core is based on seven registers.
1.4.1
Accumulator (TOS)
Because this microcontroller is a stack based machine with two on-chip stacks located in the internal RAM, all arithmetic, I/O and memory reference operations take their operands from, and return their result to the 4-bit wide expression stack. This stack is also used for passing parameters between subroutines, and as a scratchpad area for temporary storage of data. The top element of the expression stack is immediately accessible through the TOS register. The MARC4 can perform most of the operations dealing with the top of stack items (TOS and TOS-1) in a single byte, single cycle instruction.
1.4.2
Expression Stack Pointer (SP)
The 8 bit wide stack pointer SP contains the address of the next-to-top 4-bit item (TOS-1) on the expression stack, located in the internal RAM. After power-on reset the stack pointer has to be initialized to the start address of the allocated expression stack area (S0).
1.4.3
RAM Address Register (X and Y)
The 8 bit wide registers X and Y are used to address any 4-bit item in the RAM.
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IIIII IIIII IIIII IIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIIIIIII IIIIIIIIIIIIII
7 0
11
0
Program counter Return stack pointer Expression stack pointer RAM address register (X) RAM address register (Y) Top of stack register Condition code register
Interrupt enable Branch Unused Carry / borrow
RP SP X Y
00
7
0
7
0
7
0
3
0
TOS
3
0
CCR C - B I
94 8976
Figure 9. Programming model
Using either the pre-increment or post-decrement addressing mode it is comfortable to compare, fill or move arrays in the RAM area.
1.4.4
Return Stack Pointer (RP)
The return stack pointer RP points to the top element of the return stack. The 12-bit wide return stack is used for storing subroutine return addresses and keeping loop index counts. The return stack can also be used as a temporary storage area. The MARC4 instruction set supports the exchange of data between the top elements of the expression and return stack. The return stack automatically pre-increments and post-decrements in steps of 4. This means that every time a subroutine return address is stacked, 4-bit RAM locations are left unwritten. These locations are used by the qFORTH compiler to allocate 4-bit variables. After power-on reset the return stack pointer has to be initialized to FCh.
1.4.5
Program Counter (PC)
The program counter (PC) is a 12-bit register that contains the address of the next instruction to be executed by the microcontroller.
Rev. A3, 13-Jan-99
(e3505) M43C505
1.4.6 Condition Code Register (CCR)
The 4-bit wide condition code register (CCR) indicates the results of the instruction just executed as well as the state of the microcontroller. These bits can be individually tested by a program and specified action will take place as a result of their state. Each bit is explained in the following paragraphs. Carry/Borrow (C) This flag indicates that a borrow or carry out of the arithmetic logic unit (ALU) occurred during the last arithmetic operation. This bit is also affected during shift and rotate operations and the execution of SET_BCF, CLR_BCF and CCR! instructions. Zero (Z) When this bit is set, it indicates that the result of the last arithmetic or logical manipulation was zero. Branch (B) A conditional branch takes place when the branch flag was set by one of the previous instructions (e.g. a comparison operation). Instructions such as SET_BCF, TOG_BF, and CLR_BCF allow the direct manipulation of the branch flag under program control. The flag is affected by all ALU operations except CCR@, DI, SWI, RTI, and OUT. Interrupt enable (I) This flag is used to control the interrupt processing on a global basis. Resetting the interrupt enable flag (using the DI instruction) disables all interrupts. The C does not process further interrupt requests until the interrupt enable flag is set again by either executing an EI, RTI (Return-from-interrupt) instruction or entering the SLEEP mode. After power-on or an external reset the interrupt enable flag is automatically reset. The RTI instruction at the end of the $RESET routine will set the interrupt enable flag and thereby enable all interrupts.
1.4.7
Self-Check
The self test capability of the MARC4 provides the possibility of easily checking the core by executing the RAM and ROM tests after power-on reset. The RAM_TEST and ROM_TEST routines have to be included (either conditionally or unconditionally) in the $RESET routine.
Example: Different methods to implement the self test routines : $RESET >SP >RP Port0 IF RAM_Test ROM_Test THEN Reset_LCD Init_Vars ; Note: ; If the self test routines are included unconditionally care should be taken that the pattern written to Port 1 does not interfere with the application hardware. If the stimulus read from Port 0 is different from zero, TEMIC has to be informed (see ordering information). THEN S0 FCh IN 0= : $RESET DI >SP >RP RAM_Test ROM_Test ErrorFlag @0 = IF Init_Vars S0 FCh
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M43C505 (e3505)
2 Reset Modes, Interrupts, and Low Power Modes
D Variable and array initialization, and D Initialization and setup of the peripherals.
After execution of the $RESET service routine the interrupts are enabled automatically by the RTI or a previously executed EI instruction. This chapter describes the reset modes and the different interrupt capabilities of this microcontroller. The low power consumption modes are also discussed.
2.1
Reset Modes
The M43C505 has two reset modes: an active low external reset pin (NRST) and a power-on reset function.
2.1.1
External Reset (NRST)
2.2
Interrupts
The NRST input pin is used to reset the C to provide an orderly software startup procedure. When using the external reset mode, the NRST pin should be low for a minimum of two instruction cycle times.
2.1.2
Power-on Reset
The power-on reset occurs when a positive transition is detected on the power supply input pin. The power-on reset is used strictly for power turn-on conditions and should not be used to detect any drops in the power supply voltage. A power-down reset occurs when a negative transition is detected on the power supply input pin. To improve noise immunity the power-on reset has Schmitttrigger characteristics as shown in figure 31.
The M43C505 can handle interrupts of 8 priority levels (table 3). They are generated from on-chip modules (prescaler), external sources (Port 5 and interrupt pads) or synchronously from the core itself (software interrupts). Each interrupt source has a hard-wired interrupt priority and an associated interrupt service routine in the program ROM. The programmer can enable or disable all interrupts by setting or resetting the interrupt enable flag in the CCR using the EI or DI instruction. When the interrupt enable flag is reset (interrupts disabled), the execution of interrupts is inhibited but not the logging of the interrupt requests in the interrupt pending register. While interrupts are disabled (e.g. for a time critical section of code) and an interrupt is generated the interrupt will not be lost. Its execution will only be delayed until interrupts are enabled again. Interrupts are only lost when the pending register for a particular interrupt priority is still set at the time of a further interrupt transmission of the same level. The pending register is reset either on power-on reset or on completion of the corresponding interrupt service routine by executing the RTI instruction (see figures 10 and 11). The C automatically enters the SLEEP mode when the lowest priority interrupt service routine has been completed. This guarantees a maximum use of the power saving capabilities of the C. Refer to Low power modes for more information. Located in ROM at 1E0h 1C0h 180h 140h 100h 0C0h 080h 040h Max. Length [ROM bytes] 24 32 64 64 64 64 64 64 Interrupt Opcode FCh F8h F0h E8h E0h D8h D0h C8h
2.1.3
Effects on Internal Circuitry
Both reset modes guarantee a well-defined start condition of the complete microcontroller. During reset all interrupts are disabled, all pending and active interrupts are cleared, all on-chip peripherals are reset and a non-maskable interrupt request is generated. This interrupt has the absolute highest priority, having access to the microcontroller at all times. The main tasks of the reset service routine ($RESET) are:
D Stack pointer initialization, D Self test program execution,
Table 3. Interrupt priority ad address allocation map
Priority INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
Function External hardware interrupt, negative edge triggered Prescaler interrupt #2 Prescaler interrupt #1 Port 5, keyboard interrupt Software interrupts (SWI3) External hardware interrupt, negative edge triggered Software interrupt (SWI1) Software interrupt (SWI0)
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Reset corresponding active & pending bit Pending register empty ? Y SLEEP mode N
2.2.1
Interrupt Handling
The integrated interrupt controller samples all interrupt requests and latches these in the interrupt pending register. It also decodes the priority of the interrupt requests, and signals the C when a higher priority interrupt request is present. If the C (with interrupts enabled) receives the interrupt controller's signal an interrupt acknowledge cycle will be entered. During this cycle, the C saves the current PC on the return stack and loads the PC with the
Rev. A3, 13-Jan-99
IIIII IIIII IIIII IIIII
Hardware interrupt Software interrupt SLEEP mode ? N Y Wake up RC oscillator Decode interrupt & set INTx pending bit Priority decode: pending INT > active INT ? Y Set INTx active bit Continue the active INT routine Execute INTx opcodes N INT routine finished (RTI)
IIII IIII
96 12027
Figure 10. Interrupt flowchart
start address of the corresponding interrupt service routine. When the C is in the SLEEP mode it will be activated by any hardware interrupt, by the means of starting the RC oscillator and decoding the interrupt. Using the MARC4 way of interrupt transmission it is possible to transmit more than one interrupt at the same time. The transmitted interrupts are loaded into the interrupt pending register asynchronously. The priority decoder determines the interrupt with the highest priority and activates it as shown in figure 10.
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INT7
7 6 Priority level 5 4 3 2 1 0
The interrupt priority level handling versus time is shown in figure 11.
2.2.2
The interrupt latency is the time from the falling edge of the interrupt to the interrupt service routine being activated. This time is at minimum three and at maximum five instruction cycles depending on the state of the core. The highest interrupt frequency which can be reasonably handled is between 1 and 4 kHz depending on the supply voltage range (i.e. the RC oscillator frequency) and the duty cycle of the application.
2.2.3
Software interrupts are executable instructions which are supported by predefined macros named SWI0 through SWI7. The software triggered interrupt operates exactly like any hardware triggered interrupt.
14 (40)
AAAAA AAAAA AAIIIIIII AA AAIIIIIII AA AAIIIIIII AA AAII AA AIIIII AAAA AAA AAAAA AAA AAA AAAA AAA AAAA AAAA AAAA
INT7 active INT5 RTI INT5 active INT3 RTI INT2 INT3 active RTI INT2 pending
SWI0
INT2 active
RTI
INT0 pending
INT0 active
RTI Main / Autosleep
Main / Autosleep
Time
94 8978
Figure 11. Interrupt processing
2.3
Hardware Interrupts
Port 5 Interrupts
Interrupt Latency
Port 5 may generate an interrupt of priority level 4 if any of the four input lines of Port 5 is driven low. This function is disabled after power-on reset. The interrupt is enabled by writing any value to Port 5 and is automatically disabled after a read from Port 5. External interrupts The external interrupts INT2 and INT7 are negative edge triggered and have Schmitt-trigger characteristics to improve the noise immunity. As shown in figure 12, the following mask programmable options are available on the two external interrupt input pads:
Software Interrupts
D D D D
Integrated pull-up Integrated pull-down No pull-up or pull-down Active pull-up/pull-down (see figure 12b)
Rev. A3, 13-Jan-99
(e3505) M43C505
V DD * INT2 V DD * * Customer options Interrupt logic ( a)
This option is useful in applications when the external signal is forced to logic 1 or 0 for a longer period of time.
2.3.1
Interrupt Mask Register
INT7
The external interrupts INT2 and INT7 are maskable. This means INT2 or INT7 may be disabled individually while still receiving all other interrupts.
(b) Interrupt logic
INT2
Additionally, if not used as an interrupt input, INT2 can be utilized as an output. A static output level or an audio frequency square wave is selectable in output mode. The tone frequency is derived from the crystal oscillator frequency f C and can be easily calculated by the following formula: fC 24 The frequency is either 4.096 kHz or 2.048 kHz if a standard watch crystal is used. A customer option is available to select one of the two buzzer frequencies. This output mode may also be useful for trimming the crystal oscillator frequency. f BUZ
C 3
INT7 *
96 12028
Figure 12. Interrupt option diagram
Active pull-up/pull-down option When using the active pull-up/pull-down option (figure 12), a low input resistance is ensured without the DC current flow associated with a pull-up or pull-down resistor. The pull-up or pull-down function is selected depending on the current state of the Schmitt-trigger output. When this option is used the input impedance may vary as the internal pull-up or pull-down is switched in.
f +2
or
All of these actions are selected by writing a control code to Port 6 (table 4).
Table 4. Port 6 control register functions
Control Code 1111 1011 0111 0011 1010 1001 1000 0010 0001 0000
INT7 enabled enabled masked masked enabled enabled enabled masked masked masked
INT2 enabled masked enabled masked masked masked masked masked masked masked
I/O Input Input Input Input Output Output Output Output Output Output
INT2 I/O Function Negative edge triggered interrupt Negative edge triggered interrupt Negative edge triggered interrupt Negative edge triggered interrupt Output high Output low Buzzer frequency Output high Output low Buzzer frequency
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M43C505 (e3505)
2.4 Interval Timer/Prescaler Interrupts
from 128 Hz down to 1 Hz. They are selectable by writing a value of 7 to 0 into the control register at port address 15. The corresponding interrupt (INT5) can only be masked by resetting the complete prescaler. The second interrupt source (INT6) allows the selection of 5 different taps from the divider chain ranging from about 4 kHz down to 16 Hz by writing the corresponding code (Dh to 9) into the control register at port address 15. The programmable interval timer is usually driven by an external 32.768 kHz watch crystal. Using for example a 38.4 kHz crystal, it is possible to emulate an asynchronous serial interface protocol easily by software. The prescaler consists of a 15-stage divider chain with two multiplexers. They offer two interrupt sources with priority level 5 and 6. The prescaler module powers up in the reset condition which corresponds to control code Fh. The prescaler interrupt (INT5) has 8 programmable taps
Table 5. Selectable interval times for the prescaler (control Port 15)
Control Code F E D C B A 9 8 7 6 5 4 3 2 1 0
Interrupt p Source none (INT5 only) INT6 INT6 INT6 INT6 INT6 INT5 INT5 INT5 INT5 INT5 INT5 INT5 INT5 INT5
Interrupt p Frequency
fc/23 fc/25 fc/27 fc/29 f c / 2 11 fc/28 fc/29 f c / 2 10 f c / 2 11 f c / 2 12 f c / 2 13 f c / 2 14 f c / 2 15
f C = 32.768 kHz Time Interval Interrupt Frequency Reset & hold complete prescaler INT6 disabled, INT5 still active 244.14 s 4096 Hz 976.56 s 1024 Hz 3.906 ms 256 Hz 15.625 ms 64 Hz 62.5 ms 16 Hz reserved 7.81 ms 128 Hz 15.625 ms 64 Hz 31.25 ms 32 Hz 62.5 ms 16 Hz 125 ms 8 Hz 250 ms 4 Hz 500 ms 2 Hz 1s 1 Hz
The interrupt INT6 may be disabled selectively using control code Eh without affecting the interval time of the INT5 tap. The INT6 multiplexer powers up in the disabled position. The programming of the INT6 interrupt taps should be done synchronously, if different time base intervals are used temporarily (stop watch application, keyboard debouncing) or an accurate number of interrupts is required. To avoid the transmission of additional unwanted interrupts, the change of the INT6 tap should be done in a time frame of 200 s after the reception of a prescaler interrupt. As illustrated in table 5 only the INT6 tap can be disabled individually. Therefore special care has to be taken for INT5. In the case of programming the INT6 tap without previously selecting an INT5 tap (i.e. after power-on reset), an INT5 frequency of 128 Hz is set by default. Concerning the program development using INT6, the following rules should be considered:
D Always program both prescaler interrupt taps, D If only INT6 is required, select the 1 Hz tap and define
an empty INT5 routine,
D Otherwise implement a "disable" flag in the INT5 service routine.
2.4.1
Prescaler during SLEEP Mode
When the microcontroller enters the SLEEP mode, the C's internal clocks are halted. While the 32 kHz oscillator, LCD driver, and prescaler remain active, all C actions are suspended. The microcontroller exits the SLEEP mode when an interrupt is generated by the prescaler (in addition to a logic low on an external interrupt, Port 5 input pin, or an external reset).
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2.5 Low Power Modes
Two low power consumption modes of operation are available: SLEEP and STOP mode. These operating modes are initiated by executing the SLEEP instruction. Note: The SLEEP instruction is not a normal instruction as its function is dependent on the state of the interrupt pending register. SLEEP is therefore available for use within the $AUTOSLEEP and $RESET routine only. decoded and the program counter is loaded with the corresponding starting address of the interrupt or reset service routine. The MARC4's unique Auto-Sleep feature allows the C to enter the SLEEP mode automatically when the lowest priority interrupt service routine has been completed. The SLEEP mode is a shutdown condition which is used to reduce the average system power consumption in applications where the C is not fully utilised (figure 13). Using SLEEP and interrupts, the full computational speed of the core is always available. In this way, power is only consumed when needed, allowing the C to run in high speed bursts from a weak supply (battery, capacitor, or even a solar cell). Note: When TST1 is tied to VSS during power-on reset, the C activity is observable at the TCL pin (using a low capacitance probe).
2.5.1
SLEEP Mode
By executing the SLEEP instruction (in the $AUTOSLEEP routine) the microcontroller enters a low power consumption mode. In this SLEEP mode, the programmable prescaler and the LCD driver remain active, while the internal RC oscillator (C clock) is turned off causing all core processing to be stopped. It can only be kept when none of the interrupt pending or active register bits are set. During the SLEEP mode, the I bit in the condition code register is set to enable all interrupts. All other registers, memory, and parallel input/output lines remain the same. The 32-kHz crystal oscillator is not switched off, but the prescaler or the LCD driver may be disabled by the application program. This mode will continue until any interrupt or reset is sensed. At this time the event is
Calculating the average power consumption The total power consumption is directly proportional to the active time of the C. For a rough estimation of the expected average system current consumption, the following formula should be used: I SYS
+I )
SLE
I DD
T active T total
Low activity example:
Activity
Interrupt Active Sleep
Interrupt Active Sleep Average power
Interrupt
Power
High activity example:
Activity
Interrupt
Active
Interrupt
Active
Sleep
Power
Average power
94 9050
Figure 13. Average system power consumption and duty cycle
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2.5.2 STOP Mode
The lowest power consumption mode of the microcontroller is entered with the STOP operation. The current consumption of the C (without external loads) will be reduced to less than 1 A at 3 Volts. The STOP mode can be implemented by switching off the power supply of the crystal oscillator (AVDD) with one of the port output lines (refer to figure 14). Before executing the STOP routine, the prescaler should be reset and the LCD driver should be put into the BLANKING mode, because both are turned off when the 32-kHz oscillator is switched off. The internal RC oscillator is stopped by the SLEEP instruction, suspending all further internal processing. During the STOP mode, the I bit in the CCR is set to enable external interrupts. All other registers, memory, and all I/O lines remain unchanged. This continues until an external interrupt or reset is decoded. The program counter is loaded with the corresponding starting address of the interrupt or reset service routine respectively. By writing a logic 1 to the corresponding port, the interrupt or reset service routine may turn on the crystal oscillator. The oscillator's start-up time in the range of several seconds (which depends on the operating temperature and supply voltage) must be kept in mind. Therefore the occurrence of the first prescaler interrupts might not be as accurate as usual.
BPxy VDD
32 kHz 100 nF
OSCIN OSCOUT AVSS VSS
M43C505
96 12029
AVDD
Figure 14. STOP mode application
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3 Liquid Crystal Display Driver
D Programmable multiplex rate:
Direct drive, 2:1, 3:1, or 4:1 multiplex mode
This chapter describes the programming of the LCD driver. It also includes
D A discussion of a simple method of setting the LCD
power supply voltages
3.1
Display Data Register
D Information about the relationship between a typical
7-segment numeric display, the segment and backplane outputs (for 2:1, 3:1, and 4:1 multiplex)
D Waveform examples for the different drive modes.
Figure 15 is a functional block diagram of the LCD driver circuitry. The internal I/O bus is connected to the LCD control register (Port 2) and the LCD data register (Port 3). The LCD driver interface to the programmer comprises these two output ports. The LCD driver circuitry offers the following features:
The LCD data register receives the data from the C and processes it in a 4-bit wide circular 20-stage shift register. The functional block diagram (figure 15) shows the order of the segment information and the way it has to be written into the shift register (starting with the 20-th segment). A logic 1 in the shift register's bit-map indicates the ON state of the corresponding LCD segment. Similarly a logic 0 indicates the OFF state. There is a one to one correspondence between each stage of the shift register and the segment outputs, and between the individual bits of a register nibble and the backplane outputs. The LSB of each nibble correspond to the 20 segments operated with respect to backplane COM0. In multiplexed LCD applications the segment data of the second, third and fourth column of the shift register are time multiplexed with COM1, COM2 and COM3 respectively. The LCD specific segment decoding is done via qFORTH software routines, thus omitting the need for separate decoding circuitry.
D Drives up to 80 display segments D Supports 5 Volt LCD panels over the full supply
voltage range
D Built-in LCD voltage generation with temperature
compensation (-8 mV/ oC)
D Display continues when C in SLEEP mode
COM0
COM1
COM2
Control
Port2 I/O bus
MUX_RATE, BLANKING, DISPLAY
LCD drivers
SHIFT LSB
Port3
Data
MSB
20-stage shift register
VEE2 C1 C2 VEE1 V REG
94 9020
MUX_RATE, POWERSA VE
32 kHz
Prescaler
Voltage and timing generator
Figure 15. LCD driver - functional block diagram
Rev. A3, 13-Jan-99
COM3
S01
S02
S03
S04
S05
S16
S17
S18
S19
S20
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3.2 LCD Control Register
The LCD control register receives the operation mode data at Port 2 to configure the LCD driver circuitry (refer to table 6).
Table 6. LCD driver - operation modes
registers. This is especially true when the C is heavily loaded by a number of interrupt sources and the LCD update is handled as a base task. The BLANKING will be removed at the end of the data transfer by writing DISPLAY. If the DISPLAY command is not given, the BLANKING remains which allows the easy implementation of a blinking display. When using the MASK/SHIFT term, only nibbles requiring an update need to be software decoded and written to the LCD data register. The data to be retained is simply shifted back to its original position, whilst new data nibbles are inserted in the appropriate position (refer to figure 15). As an example for the effective use of the MASK/SHIFT term, the implementation of a 6 digit (3:1 multiplex) LCD panel test is described.
Control Code 0 1 2 3 4 5 6
Operation Mode DIRECT DRIVE 2:1 MULTIPLEX 3:1 MULTIPLEX DISPLAY CLEAR/INIT (4:1 MULTIPLEX) MASK/SHIFT BLANKING
3.2.1
Initializing the LCD Driver
D Setup the LCD driver for 3:1 MULTIPLEX. D Switch on all segments of the leading 7 segment digit
(including the attenuator, see figure 21) with a complete LCD display update.
At power-on reset the LCD driver circuitry is set automatically into BLANKING and 4:1 MULTIPLEX drive mode. After any reset condition, a proper operation of the LCD driver is ensured by writing the following control codes into the LCD control register:
D After (half of) a second, write MASK/SHIFT to the
LCD control register. Write three dummy values to the LCD data register to support the shift clock pulses. This operation will scroll the digit one position to the right.
D CLEAR/INIT D Multiplex drive mode (if not 4:1 MULTIPLEX)
Four terms can be used to set the multiplex rate (refer to table 6). The CLEAR/INIT term initializes the LCD driver, setting it into the 4:1 multiplex drive mode. Therefore no extra control code is needed for 4:1 MULTIPLEX. After any hardware reset the contents of the LCD display registers are undefined and should be initialized with the following instruction sequence:
D After a total of five operations, the digit appears in the
right-most position and the (BLANKING or) DISPLAY term should be given to the control register to overwrite the MASK/SHIFT multiplexer configuration.
3.3
LCD Voltage and Timing Generator
D Write BLANKING to the LCD control register D Write zero 20 times to the LCD data register D Write DISPLAY to the LCD control register
3.2.2 LCD Driver - Modes of Operation
In normal time keeping applications the DISPLAY command might be given only once at the end of the first complete LCD display update (e.g. "Mo 12:00"). Afterwards a total display change consists only of 20 consecutive nibbles written to the LCD data register. The BLANKING term causes a blank display and might be necessary before each new data transfer to the display
The LCD voltage generator circuitry boosts the regulated liquid crystal display voltage (VREG) to the doubled and tripled voltage components (VEE1, VEE2) required by multiplexed liquid crystal displays. These voltage levels are applied to the driver circuitry (see figure 15). Most 5 Volt LCD panels have a temperature coefficient of -8 mV/oC. The temperature compensated reference for the LCD voltage booster circuitry (VREG), has the task of meeting this requirement directly, so the user gets the best LCD contrast over the full operating temperature and supply voltage range. The external components for the LCD voltage generation (one pump and two storage capacitors) should be connected to the C as shown in figure 16 .
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100 nF V EE2 C1 100 nF C2 100 nF V EE1 V REG V SS
94 9021
for 4 segments per segment driver. The maximum capacitive load per segment driver could be up to 4 nF. Example: Based on a total height of 30 mm, a normal segment may have the dimensions of 15 mm x 4 mm = 60 mm2. Therefore the capacitance/mm2 of the selected LCD panel has to be 1.65 nF/60 mm2 27 pf/mm2.
3.4
Direct Drive Mode
The static LCD drive mode is used when a single backplane is provided at the LCD. The LSB of each stage of the display shift register directly maps to the corresponding segment driver. Sample backplane and segment drive waveforms for this mode are shown in figure 17. The following formulas are valid in the DIRECT DRIVE mode at any instant (t): Vstate1 (t) = VS01(t) - VCOM0 (t) Vstate2 (t) = VS02 (t) - VCOM0 (t) Von(rms) = VEE2 V off(rms)
Figure 16. External components
For very small LCD panels the capacitor values may be reduced from 100 nF to 47 nF. The user has to connect the C and the LCD as it will be in the final product in order to select the capacitor value. To examine the LCD driver waveforms an oscilloscope with a low capacitance probe should be used.
3.3.1
Maximum LCD Drive Capability
As a design guideline for large LCD panels, use the following basic formula to describe the flatening of the LCD segment and backplane driver outputs:
+ V3 + V
EE2
REG
t=RxC
Assuming the 1/4 duty, 1/3 bias LCD drive method up to 80 segments on the LCD panel is descibed in figure 26. The frame frequency at 1/4 duty is given as 64 Hz (16 ms) and each backplane will be active for 4 ms. The decrease of the rise and fall time at the output waveform signals to be seen at higher LCD segment loads is given to 100 ms. Any higher capacitive load will increase the average DC offset voltage. Please check this important parameter with your LCD supplier too. To improve the drive capabilty of the LCD driver the storage capacitors at VEE1 and VEE2 has to be increased to 220 nF. Drive Capability of Each Backplane (COM0...3) RBPOmax = 3 kW 100 ms C BPmax 3 kW
==> Contrast ratio = 3.0
(a) Waveform at driver Time frame 128 Hz LCD segments
V EE2 COM0 VSS S01
state1 (ON)
state2 (OFF)
S02
(b) Resultant waveforms at LCD segment V EE2
+
+ 33 nF
state1
0 -VEE2
for 20 segments per backplane driver. Therefore the maximum capacitive load per segment is around 1.6 nF. Drive Capability of Segment Outputs (S01...S20) RSEGOmax = 6 kW 100 ms C SEGmax 6 kW
state2
+
+ 16.5 nF
V REG 0 -VREG
94 9023
Figure 17. Direct drive mode waveforms
Rev. A3, 13-Jan-99
21 (40)
M43C505 (e3505)
3.5 2:1 Multiplex Drive Mode
Figure 18 shows the connection of a 2:1 multiplex 5 digit LCD panel having the numeric display pattern shown in figure 19, the segment outputs (S01-S20), and the backplane outputs (COM0, COM1). In the example "456.78" is displayed on the LCD panel and the corresponding contents of the display data register is shown.
94 9024
Backplane and segment drive waveforms for this mode are shown in figure 20.
Figure 18. 2:1 Multiplex 7 segment digit
I/O bus
LCD data shift register
0 0 x x 1 0 x x 1 1 x x 1 0 x x 0 1 x x 1 1 x x 0 1 x x 1 0 x x 1 1 x x 1 1 x x 0 1 x x 1 1 x x 0 0 x x 1 1 x x 1 0 x x 1 0 x x 1 1 x x 1 1 x x 1 1 x x 1 0 x x
Data register
Bit0 Bit1
LCD panel
Figure 19. 2:1 Multiplexer LCD panel connection
22 (40)
Rev. A3, 13-Jan-99
N.C. N.C.
94 9025
COM0 COM1 COM2 COM3
S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01
(e3505) M43C505
(a) Waveforms at driver
Time frame 64 Hz COM0 VEE2 VEE1 VREG VSS
LCD segments
state1 state2
COM1
S01
S02
(b) Resultant waveforms at LCD segment
V EE2 V EE1 V REG Segment ON Segment OFF
state1
0 -VREG -VEE1 -VEE2
94 9026
state2
0
Figure 20. Waveforms for 2:1 multiplex drive mode
The following formulas are valid in the 2:1 multiplex drive mode at any instant (t): Vstate1 (t) = VS01(t) - VCOM0 (t) and Vstate2 (t) = VS01 (t) - VCOM1 (t) V on(rms)
+ V3
EE2
5
+ 0.745 V
EE2
and V off(rms)
+ V3
EE2
Contrast ratio = Von(rms) / Voff(rms) = 2.23
Rev. A3, 13-Jan-99
23 (40)
M43C505 (e3505)
3.6 3:1 Multiplex Drive Mode
S n+1 Sn+2 a f g e d
Backplane and segment drive waveforms for this mode are shown in figure 23. Attenuator (n.c.) COM0 Figure 21 shows the connection of a 3:1 multiplex 6 3/4 digit LCD panel having the numeric display pattern shown in figure 22, the segment outputs (S01-S20), and the backplane outputs (COM0-COM2). In the example, "123456.7" is displayed (with a max. displayable value of "3999999") and the corresponding contents of the LCD display data register is shown.
b c
Sn
a f g e
DP
b c COM1 d
COM2 DP
94 9027
Figure 21. 3:1 multiplex 7 segment digit
I/O bus
LCD data shift register
0 0 0 x 1 1 0 x 0 0 x x 1 1 1 x 1 0 0 x 0 0 x x 1 1 1 x 1 1 0 x 1 0 x x 0 1 0 x 1 1 0 x 1 0 x x 1 1 1 x 0 1 0 x 1 1 x x 1 1 1 x 0
1 f 1 a 1 b
Data register
Bit0 Bit1 Bit2
1 0 e 0g 1 c 1 x
x x 0 d 0 x
x
DP
LCD panel
Figure 22. 3:1 Multiplexer LCD panel connection
24 (40)
Rev. A3, 13-Jan-99
COM0 COM1 COM2 N.C. COM3
94 9028
S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01
(e3505) M43C505
(a) Waveforms at driver
43 Hz Time frame COM0 V EE2 V EE1 V REG V SS state1 state2 COM1 LCD segments
COM2
S01
S02
S03 Segment ON Segment OFF
(b) Resultant waveforms at LCD segment
V EE2 V EE1 V REG 0 -VREG -VEE1 -VEE2 0 Figure 23. Waveforms for 3:1 multiplex drive mode
state1
state2
94 9029
The following formulas are valid in the 3:1 multiplex drive mode at any instant (t): Vstate1 (t) = VS01(t) - VCOM0 (t) and Vstate2 (t) = VS01 (t) - VCOM1 (t) V EE2 V EE2 V on(rms) 33 0.638 V EE2 and V off(rms) 9 3 Contrast ratio = Von(rms) / Voff(rms) = 1.915
+
+
+
Rev. A3, 13-Jan-99
25 (40)
M43C505 (e3505)
3.7 4:1 Multiplex Drive Mode
Sn Figure 24 shows the connection of a 4:1 multiplex 10 digit LCD panel having the numeric display pattern shown in figure 25, the segment outputs (S01-S20), and the backplane outputs (COM0-COM3). In the example, "123456.7890" is displayed and the corresponding contents of the LCD display data register is shown. Backplane and segment drive waveforms for this mode are shown in figure 26.
a f g e d
Sn+1
COM0
a f g b c d
COM3 DP
94 9030
b
COM2 DP
COM1
c
e
Figure 24. 4:1 Multiplex 7 segment digit
I/O bus LCD data shift register
0 0 0 0 0 1 1 0 0 1 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 1 1 1 0 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 1 0 0 1 1f 0 1 g 1 1 e 0 1d 1 1 1 0 a b c
Data register
Bit0 Bit1 Bit2 Bit3
DP
S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01
LCD panel
Figure 25. 4:1 Multiplexer LCD panel connection
26 (40)
Rev. A3, 13-Jan-99
COM0 COM1 COM2 COM3
94 9031
(e3505) M43C505
(a) Waveforms at driver
64 Hz VEE2 COM0 V EE1 V REG V SS COM1 state2 COM2 Time frame LCD segments
state1
COM3
S01
S02
S03
S04
Segment ON Segment OFF
(b) Resultant waveforms at LCD segment
state1 V EE2 0 -V EE2 state2 V REG 0 -V REG Figure 26. Waveforms for 4:1 multiplex drive mode
94 9032
The following formulas are valid in the 4:1 multiplex drive mode at any instant (t): Vstate1 (t) = VS01(t) - VCOM0 (t) and Vstate2 (t) = VS01 (t) - VCOM1 (t) V on(rms)
+ V3
EE2
3
+ 0.577 V
EE2
and V off(rms)
+ V3
EE2
Contrast ratio = Von(rms) / Voff(rms) = 1.732
Rev. A3, 13-Jan-99
27 (40)
M43C505 (e3505)
4
4.1
Electrical Specification
Absolute Maximum Ratings
Symbol VDD VIN tshort Tamb Tstg JA Tsld Value -0.3 to +7.0 VSS-0.3 VIN VDD+0.3 indefinite -20 to +80 -40 to +125 70 260 (t 10 sec) Unit V V sec C C C/W C
All voltages are given relative to VSS. The circuit is protected against supply voltage reversal for typically 5 minutes. Parameters Supply voltage Input voltage (on any pin) Output short circuit duration Operating temperature range Storage temperature range Thermal resistance (PLCC) Maximum solder temperature Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any condition above those indicated in the operational section of these specification is not implied. Exposure to absolute maximum rating condition for an extended period may affect device reliability. All inputs
and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize built-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., VDD).
4.2
DC Operating Characteristics, VDD = 3 V
Supply voltage VDD = 3.0 V, VSS = 0 V, Tamb = +25C unless otherwise specified. All voltage levels are measured with reference to VSS and current flowing into the device is positive. Typical parameters represent the statistical mean values. Parameters Supply voltage Active current Sleep current Supply current quotient RC oscillator frequency q y (system clock) Test Conditions / Pins Note 1 Note 2 Note 3 Note 5, 8 (see figure 29) VDD = 2.4 V Symbol VDD IDD ISLE
I DD SYSCL
Min. 2.4 2.0 0.7 0.9 0.5
Typ. 3.0 1.4 3.0 0.8 1.75 0.75 1.8 -100 20 5
Max. 3.6 2.5 5.0 0.9 2.8
Unit V mA
mA
mA MHz
SYSCL
MHz MHz V mV nA pF V V nA nA pF
Internal power-on reset POR voltage Note 4, 8 (see figure 31) VPOR POR voltage hysteresis Note 8 VPOR Output pads Hi-Z leakage current Open drain IOZ Output capacitance Note 8 COUT Input pads (except NRST and OSCIN under test conditions) Input voltage high VIH Input voltage low VIL Input current low VIN = VSS; no pull up IILO Input current high VIN = VDD IIH Input capacitance Note 8 CIN
2.2
100 10 VDD 0.2*VDD 100 100 10
0.8*VDD VSS
20 20 5
28 (40)
Rev. A3, 13-Jan-99
(e3505) M43C505
Parameters Test Conditions / Pins Symbol NRST and OSCIN input pads under test conditions Input voltage high VIH Input voltage low VIL Bidirectional Ports 0, 1, 4, outputs NST, OD and buzzer Input current low **) VIN = VSS IIL Output current high VOH = 2.4 V IOH Output current low VOL = 0.6 V IOL Input Port 5 Input current low **) VIN = VSS IIL Min. VDD VSS -0.8 0.8 1.5 -6 -1.6 -1.3 2.4 -13 -8 -6 - 11 1.1 Typ. Max. VDD VSS -3 Unit V V A mA mA A A A V
NRST input
-20 -16 -20
Input current low VIN = VSS Interrupt Schmitt-trigger input INT2, INT7 Input current low **) VIN = VSS Negative going threshold Note 8 voltage **)
IIL IIL VT-
IIL values are only valid if the pull-up resistor is optioned in.
4.3
DC Operating Characteristics, VDD = 5 V
Supply voltage VDD = 5.0 V, VSS = 0 V, Tamb = +25C unless otherwise specified. All voltage levels are measured with reference to VSS and current flowing into the device is positive. Typical parameters represent the statistical mean values. Parameters Supply voltage Active current Sleep current Supply current quotient RC oscillator frequency Internal power-on reset Power-on reset voltage POR voltage hysteresis Test Conditions / Pins Note 1 Note 2 Note 3, 8 Note 5, 8 Note 4, 8 (see figure 31) Note 8 Symbol VDD IDD ISLE
I DD SYSCL
Min. 2.4 3 2
Typ. 5 7 7 2 3.5 1.8 -100 20 5
Max. 5.5 15 10 2.1
Unit V mA A
mA MHz
SYSCL VPOR VPOR
MHz 2.2 V mV nA pF V V nA nA pF V V
Output pads
Hi-Z leakage current Open drain IOZ Output capacitance Note 8 COUT Input pads (except OSCIN and NRST under test conditions) Input voltage high VIH Input voltage low VIL Input current low VIN = VSS; no pull up IILO Input current high VIN = VDD IIH Input capacitance Note 8 CIN NRST and OSCIN input pads under test conditions Input voltage high VIH Input voltage low VIL
300 10 VDD 0.2*VDD 300 300 10 VDD VSS
0.8*VDD VSS
20 20 5
VDD VSS
Rev. A3, 13-Jan-99
29 (40)
M43C505 (e3505)
Parameters Test Conditions / Pins Symbol Bidirectional Ports 0, 1, 4, outputs NST, OD and buzzer Input current low **) VIN = VSS IIL Output current high VOH = 4 V IOH Output current low VOL = 1 V IOL Input port 5 Input current low **) VIN = VSS IIL Min. -3 -1.2 2.5 -25 Typ. -5.5 -2 3.5 -45 -25 -20 -37.5 1.6 Max. -8 Unit A mA mA A A A V
NRST input
-60 -50 -60
Input current low VIN = VSS Interrupt Schmitt-trigger input INT2, INT7 Input current low **) VIN = VSS Negative going threshold Note 8 voltage **)
IIL IIL VT-
IIL values are only valid if the pull-up resistor is optioned in.
4.4
DC Operating Characteristics, VDD = 2.4 to 5.5 V, Tamb = +25C
Test Conditions / Pins Symbol Segment outputs: S01 ... S20 Backplane outputs: COM0 ... COM3 Note 6 VREG VREG = 1650 mV VEE1 VREG = 1650 mV VEE2 Note 8 TREG 4:1 multiplex 3:1 multiplex 2:1 multiplex Direct drive VSEG = 100 mV; Note 8 VBP = 100 mV; Note 8 Note 8 CL = 10 pF Note 8 Note 8 AVDD = 100 mV; Note 8 AVDD = 3.0 V fBP Min. Typ. Max. Unit
Parameters LCD driver [5V LCD panel] Regulated voltage Doubler voltage Tripler voltage Temperature compensation relative to VREG; Backplane frequency p q y
1500 3000 4500 -7
1650 3300 4850 -8 64 43 64 128 45 4.5 2.25 50 32,768 20 23.5 0.1 2
1800 3600 5400 -9
mV mV mV mV/C Hz Hz Hz Hz k k mV Hz pF pF
Segment output resistance Backplane output resistance Average DC offset Quartz oscillator Frequency Integrated input capacitance Integrated output capacitance Stability Start-up time
R SO R BO VDC fC CIN COUT f/f tSQ
35 3.5 1.7
6 3 100
1 4
ppm sec
30 (40)
Rev. A3, 13-Jan-99
(e3505) M43C505
4.5 DC Electrical Characteristics, VDD = 3 V
Test Conditions / Pins Note 1 Note 2 Note 3 Note 5 VDD = 2.4 V Symbol IDD ISLE
I DD SYSCL
VDD = 3 V10%, VSS = 0 V, Tamb = -10C to +75C, unless otherwise specified. Parameters Active current Sleep current Supply current quotient RC oscillator frequency q y (system clock) Min. Typ. 1.5 4 0.8 0.8 0.4 1.2 -0.6 -0.7 1.5 -5 -3 -5 1.6 0.75 1.8 -1.6 -1.4 2.5 -15 -8 -12 2.4 - 3.2 - 2.1 3.5 - 25 - 15 - 20 Max. 3 7 0.9 Unit mA A
mA MHz
SYSCL
MHz MHz V A mA mA A A A
Internal power-on reset POR voltage Note 4 Bidirectional Ports 0, 1, 4 outputs NST, OD and buzzer Input current low **) VIN = VSS Output current high VOH = 2.4 V Output current low VOL = 0.6 V Input Port 5 Input current low **) VIN = VSS NRST input Input current low VIN = VSS Interrupt Schmitt-trigger input INT2, INT7 Input current low **) VIN = VSS
**)
VPOR IIL IOH IOL IIL IIL IIL
IIL values are only valid if the pull-up resistor is optioned in.
Notes: D All values shown reflect average measurements. D Typical values at midpoint of voltage range, +25C only.
D Data is for design guidance only and is not tested for,
or guaranteed by TEMIC.
4.6
DC Electrical Characteristics, VDD = 5 V
Test Conditions / Pins Note 1 Note 2 Note 3 Symbol IDD ISLE
I DD SYSCL
VDD = 5 V10%, VSS = 0 V, Tamb = -10C to +75C, unless otherwise specified. Parameters Active current Sleep current Supply current quotient Min. Typ. 8 7 2 3.5 1.8 - 5.5 -2.2 3.7 Max. 15 11 2.5 8 2.4 -9.0 -4.0 6.0 Unit mA A
mA MHz
RC-oscillator frequency Note 5 SYSCL Internal power-on reset POR voltage Note 4 VPOR Bidirectional Ports 0, 1, 4, outputs NST, OD and buzzer Input current low **) VIN = VSS IIL Output current high VOH = 4 V IOH Output current low VOL = 1 V IOL
1.5 1.2 -2.5 -1.0 2.0
MHz V A mA mA
Rev. A3, 13-Jan-99
31 (40)
M43C505 (e3505)
Parameters Test Conditions / Pins Input Port 5 Input current low **) VIN = VSS NRST input Input current low VIN = VSS Interrupt Schmitt-trigger input INT2, INT7 Input current low **) VIN = VSS
**)
Symbol IIL IIL IIL
Min. -15 -10 -15
Typ. -45 -25 -40
Max. -70 -70 -70
Unit A A A
IIL values are only valid if the pull-up resistor is optioned in.
Notes: D All values shown reflect average measurements. D Typical values at midpoint of voltage range, +25C only.
D Data is for design guidance only and is not tested for,
or guaranteed by TEMIC.
10 9 8 I OH ( mA ) 6 5 4 3 2 1 0 0 0.5 1.0 VDD-VOH ( V ) 1.5 2.0
96 12030
5.0 4.5 4.0 VDD = 5 V f SYSCL ( MHz ) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2 2.5 3.0 3.5 4.0 4.5 5.0 5.5
96 12032
7
VDD = 3 V
VDD ( V )
Figure 27. Typical IOH vs. VDD-VOH for all ports
10 9 8 6 5 4 3 2 1 0 0 0.5 1.0 VOL ( V ) 1.5 2.0
96 12031
Figure 29. Typical system clock frequency SYSCL vs. supply voltage (internal RC oscillator)
6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -20
VDD = 5 V
VDD = 3 V
f SYSCL ( MHz )
7 IOL ( mA)
VDD = 5 V
VDD = 3 V
VDD = 2.4 V 0 20 40 60 80
96 12033
Tamb ( C )
Figure 28. Typical IOL vs. VOL for all ports
Figure 30. Typical SYSCL frequency vs. temperature
32 (40)
Rev. A3, 13-Jan-99
(e3505) M43C505
2.2 2.1 2.0 1.9 VPOR ( V ) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 -20 -10 0 10 20 30 40 50 60 70 80 Tamb ( _C )
96 12034
Hysteresis VPOR
VPower down
Figure 31. Power-on reset voltage vs. temperature
Note 1: Maximum active current (IDD) This is the current observed at the VSS pin with the crystal oscillator, the LCD driver and C core permanently active. No output loads, all input ports and interrupt inputs connected to VDD and the prescaler is reset. This mode can be achieved by connecting the NRST pin to VSS. The average system current of an application can be estimated with the formula: ISYS whereby Duty cycle Active x 100% + (Sleep timetimeActive time) )
The frequency of the integrated RC oscillator depends on the supply voltage as well as on the process parameters (i.e. sum of threshold voltages). Note 4: Power-on reset voltage (VPOR) This is the supply voltage, which must be exceeded for the internal power on reset circuit to be released. The switching function can be observed on the NRST pin. Note 5: Core oscillator frequency (fSYSCL) The RC oscillator provides the central clocking of the core and the frequency varies with supply voltage and temperature to track the optimum performance of the C. This frequency can be measured on the TCL pin by connecting the NRST and TST1 pins to VSS. Note 6: LCD voltages are measured with - 100 nF capacitor between C1 and C2 - 100 nF capacitor between VEE1 and VSS - 100 nF capacitor between VEE2 and VSS. A load capacitance of 200 pF is connected between each backplane and VSS. The regulated and temperature compensated LCD voltage VREG can also be supplied from an external voltage source through the VREG pin, as long as the externally supplied voltage is larger than the internally generated voltage. It is also possible to supply all three LCD voltage levels through the pads VREG, VEE1 and VEE2 as it is done under production test conditions. Note 8: Measurement not subject to production test.
+ ISLE ) Duty cycle 100%
x I DD
IDD = 1.4 mA ; ISLE = 4 mA at 3 Volts. In 'time keeping mode' the duty cycle is less than 1%, which gives a current consumption of about 18 A at 3 V. Note 2: Sleep current (ISLE) This is the current taken with the crystal oscillator and the LCD driver active, the prescaler reset, the mC core in SLEEP mode and all input ports, bidirectional ports (if in input mode) and interrupts connected to VDD. This state can, unless catered for in the application program, only be permanently achieved under production test conditions. Note 3: Supply current quotient Normalized active current relative to the core's operation frequency SYSCL.
Rev. A3, 13-Jan-99
33 (40)
M43C505 (e3505)
5 Mechanical Data
in figure 2, page 2. The 64 pin ceramic DIL package used for emulation and prototyping purposes is also included. This chapter contains the pad layout and pad coordinates. The pin assignments for the 64 pin plastic QFP is shown
5.1
Emulation Package
The pin-out of the emulation and prototype devices are compatible to the piggyback device M40C505
BP42 BP41 BP40 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01 COM3 COM2 COM1 COM0 V EE1 C1 C2 EE2 V REG V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53
BP43 V SS TCL TST1 TST2 OSCIN N.C. N.C. N.C. AVDD N.C. AVSS OSCOUT NRST BP10 BP11 BP12 BP13 BP00 BP01 OD NST BP02 N.C. BP03 I P50 I P51 I P52 I P53 INT2 V DD INT7
96 12036
M43C505 M45C535
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Figure 32. M43C505 / M45C535 in 64 pin ceramic DIL
34 (40)
Rev. A3, 13-Jan-99
(e3505) M43C505
5.2 Pad Layout
COM1 S03 S13 S01 S05 S07 S09 S11 S14 S06 S08 COM0 COM2 COM3 S02 S04 S10 S12 S15 V EE1 C1 C2 V EE2 V REG INT7 V DD INT2 IP53 IP52 IP51 IP50 BP03 S16 S17 S18 S19 S20 BP40
M43C505 M43C505F
BP41 BP42 BP43 VSS TCL TST1 TST2 OSCIN AV DD
BP02 NST OD BP12 BP01 BP00 BP13 BP11 BP10 OSCOUT AV SS NRST
96 12037
Figure 33. M43C505 pad layout
5.3
Pad Coordinates
M43C505: The M43C505 is available in die form for COB mounting. Therefore the substrate, i.e. the backside of the die, should be connected to VSS. Die size: Pad size: Thickness: 3.84 x 3.59 mm = 13.8 mm2 (incl. scribe) 100 x 100 m 480 25 m (= 19 1 mil)
M43C505F: The M43C505D is available in bar die form for COB mounting only. Therefore the substrate, i.e. the backside of the die, should be connected to VSS. Die size: Pad size: Thickness: 3.84 x 3.57 mm = 13.7 mm2 (incl. scribe) 100 x 100 m 480 20 m
Rev. A3, 13-Jan-99
35 (40)
M43C505 (e3505)
Table 7. Pad coordinates M43C505
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Name BP02 NST OD BP01 BP00 BP13 BP12 BP11 BP10 NRST OSCOUT AVSS AVDD OSCIN TST2 TST1 TCL VSS BP43 BP42 BP41 BP40 S20 S19 S18 S17 S16 S15 S14 S13
X Point 0 202.0 380.8 556.8 889.6 1065.6 1364.4 1540.4 1847.2 2023.2 2189.2 2467.2 3333.6 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3070.0 2904.0
Y Point 0 0 0 0 0 0 0 0 0 0 0 0 0 184.4 360.4 526.4 702.4 868.4 1189.2 1488.0 1664.0 1962.8 2188.0 2354.0 2530.0 2696.0 2872.0 3038.0 3036.8 3036.8
No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Name S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01 COM3 COM2 COM1 COM0 VEE1 C1 C2 VEE2 VREG INT7 VDD INT2 IP53 IP52 IP51 IP50 BP03
X Point 2728.0 2562.0 2386.0 2220.0 2044.0 1878.0 1702.0 1536.0 1360.0 1194.0 1018.0 852.0 676.0 342.0 166.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Y Point 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 2829.0 2653.0 2274.2 2098.2 1932.2 1756.2 1590.2 1424.2 1248.2 1034.2 738.8 524.8 332.8
36 (40)
Rev. A3, 13-Jan-99
(e3505) M43C505
Table 8. Pad coordinates M43C505F
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Name BP02 NST OD BP01 BP00 BP13 BP12 BP11 BP10 NRST OSCOUT AVSS AVDD OSCIN TST2 TST1 TCL VSS BP43 BP42 BP41 BP40 S20 S19 S18 S17 S16 S15 S14 S13
X Point 0 194.0 380.8 556.8 889.6 1065.6 1364.4 1540.4 1847.2 2023.2 2189.2 2467.2 3333.6 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3130.4 2964.4
Y Point 0 0 0 0 0 0 0 0 0 0 0 0 0 184.4 360.4 526.4 702.4 868.4 1189.2 1488.0 1664.0 1962.8 2188.0 2354.0 2530.0 2696.0 2872.0 3038.0 3036.8 3036.8
No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Name S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01 COM3 COM2 COM1 COM0 VEE1 C1 C2 VEE2 VREG INT7 VDD INT2 IP53 IP52 IP51 IP50 BP03
X Point 2788.4 2622.4 2446.4 2280.4 2104.4 1938.4 1762.4 1596.4 1420.4 1254.4 1078.4 912.4 736.4 342.0 166.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Y Point 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 3036.8 2829.0 2653.0 2274.2 2098.2 1932.2 1756.2 1590.2 1424.2 1248.2 1034.2 738.8 524.8 332.8
Note: Pad coordinates printed as bold numbers identify modified pad positions compared to the e3505 and M43C505 design.
Rev. A3, 13-Jan-99
37 (40)
M43C505 (e3505)
6 Appendix M45C535
The M45C535 is especially designed for low volumes, prototyping of M43C505 with fast turn-around times of less than one month. The M45C535 is functionally and electrically compatible to the high volume standard M43C505. The M45C535 (e3535) is available either as a packaged part (QFP64) or in bare die form for COB mounting. In the latter case, the substrate, i.e. the backside of the die, should be connected to VSS. Die size: Pad size: Thickness: 3.84 x 4.41 mm = 16.9 mm2 (incl. scribe) 100 x 100 m 480 25 m (= 19 1 mil)
6.1
Pad Layout
S03 S13 S01 S05 S07 S09 S11 S15 S14 S06 S08 COM3 S02 S04 S10 S12 S16 COM2 COM1 COM0 V EE1 C1 C2 V EE2 V REG INT7 V DD INT2 IP53 IP52 IP51 IP50 BP03 S17 S18 S19 S20 n.c. n.c. n.c. n.c.
M45C535 ( e3535 )
BP40
BP41 BP42 BP43 VSS TCL TST1 TST2 OSCIN AV DD
BP02 NST OD BP12 BP01 BP00 BP13 BP11 BP10 OSCOUT AV SS NRST
96 12038
Figure 34. M45C535 pad layout
38 (40)
Rev. A3, 13-Jan-99
(e3505) M43C505
6.2
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Pad Coordinates
Name BP02 NST OD BP01 BP00 BP13 BP12 BP11 BP10 NRST OSCOUT AVSS AVDD OSCIN TST2 TST1 TCL VSS BP43 BP42 BP41 BP40 S20 S19 S18 S17 S16 S15 S14 S13 X Point 0 202.0 380.8 556.8 889.6 1065.6 1364.4 1540.4 1847.2 2023.2 2189.2 2467.2 3333.6 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3340.0 3070.0 2904.0 2728.0 2562.0 Y Point 0 0 0 0 0 0 0 0 0 0 0 0 0 184.4 360.4 526.4 702.4 868.4 1242.8 1520.4 1696.4 1974.0 3051.6 3227.6 3393.6 3569.6 3852.0 3852.0 3852.0 3852.0 No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01 COM3 COM2 COM1 COM0 VEE1 C1 C2 VEE2 VREG INT7 VDD INT2 IP53 IP52 IP51 IP50 BP03 X Point 2386.0 2220.0 2044.0 1878.0 1702.0 1536.0 1360.0 1194.0 1018.0 852.0 676.0 510.0 334.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Y Point 3852.0 3852.0 3852.0 3852.0 3852.0 3852.0 3852.0 3852.0 3852.0 3852.0 3852.0 3852.0 3852.0 3852.0 3644.0 3468.0 3302.0 3126.0 2648.0 2472.8 2306.8 1756.2 1590.2 1424.2 1248.2 1034.2 738.8 524.8 332.8
Table 9. Pad coordinates M45C535
Rev. A3, 13-Jan-99
39 (40)
M43C505 (e3505)
7 Ordering Information
Please insert ROM CRC and select the option setting from the list below. BP40 CMOS INT2 Open drain Pull-up No pull-up BP41
BP42
BP43
IP50 IP51 IP52 IP53
-
CMOS Open drain Pull-up No pull-up CMOS Open drain Pull-up No pull-up CMOS Open drain Pull-up No pull-up Pull-up No pull-up Pull-up No pull-up Pull-up No pull-up Pull-up No pull-up
INT7
OSCIN OSCOUT Buzzer Package
-
Pull-up No pull-up Pull-down Active pull-up/pull-down Pull-up No pull-up Pull-down Active pull-up/pull-down Internal CAP No CAP Internal CAP No CAP 2.048 kHz (default) 4.096 kHz DIT 64 pin QFP File: __________.HEX CRC type: 16-bit/Short CRC: _________ hex Stimulus at Port 0: ______
ROM
Selftest
Approval :
Date: __.__.__
Signature: _______________
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2594, Fax number: 49 ( 0 ) 7131 67 2423
40 (40)
Rev. A3, 13-Jan-99

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Price & Availability of M43C505

Part #	Manufacturer	Description	Price	BuyNow Qty.
M43C505F020DIT	tfk	Microcontroller, 4-Bit, MROM, MARC4 CPU, 8MHz, CMOS, PQFP64		921

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