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January 1998 NDS8426A Single N-Channel Enhancement Mode Field Effect Transistor General Description SO-8 N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. Features 10.5 A, 20 V. RDS(ON) = 0.0135 @ VGS= 4.5 V. RDS(ON) = 0.016 @ VGS= 2.7 V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. ___________________________________________________________________________________________ 5 6 7 8 4 3 2 1 ABSOLUTE MAXIMUM RATINGS T A = 25C unless otherwise noted Symbol VDSS VGSS ID PD Parameter Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed Maximum Power Dissipation (Note 1a) (Note 1b) (Note 1c) (Note 1a) NDS8426A 20 8 10.5 30 2.5 1.2 1 -55 to 150 Units V V A W TJ,TSTG RJA RJC Operating and Storage Temperature Range C THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) 50 25 C/W C/W (c) 1998 Fairchild Semiconductor Corporation NDS8426A Rev.B1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS IGSSF IGSSR VGS(th) RDS(ON) Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Gate - Body Leakage, Forward Gate - Body Leakage, Reverse Gate Threshold Voltage Static Drain-Source On-Resistance VGS = 0 V, ID = 250 A VDS = 16 V, VGS = 0 V TJ= 55C VGS = 8 V, VDS = 0 V VGS = -8 V, VDS= 0 V VDS = VGS, ID = 250 A TJ= 125C VGS = 4.5 V, ID = 10.5 A TJ= 125C VGS = 2.7 V, ID = 10 A ID(on) gFS Ciss Coss Crss tD(on) tr tD(off) tf Qg Qgs Qgd On-State Drain Current Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 10 V, ID = 10.5 A, VGS = 4.5 V VDD = 5 V, ID = 1 A, VGEN = 4.5 V, RGEN = 6 VGS = 4.5 V, VDS = 5 V VDS = 5 V, ID = 10.5 A VDS = 10 V, VGS = 0 V, f = 1.0 MHz 30 43 2150 890 165 11 26 145 40 43 7 8 30 55 220 100 60 0.4 0.3 0.6 0.5 0.012 0.017 0.014 20 1 10 100 -100 1 0.8 0.0135 0.024 0.016 A S pF pF pF ns ns ns ns nC nC nC V A A nA nA V ON CHARACTERISTICS (Note 2) DYNAMIC CHARACTERISTICS SWITCHING CHARACTERISTICS (Note 2) NDS8426A Rev.B1 ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Symbol IS VSD Notes: 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user's board design. Parameter Continuous Source Diode Current Drain-Source Diode Forward Voltage Conditions Min Typ Max 2.1 Units A V DRAIN-SOURCE DIODE CHARACTERISTICS VGS = 0 V, IS = 2.1 A 0.6 1.2 (Note 2) PD (t) = T J -T A R JA(t) = T J -T A R JC +R CA(t) = I 2 (t) x R DS(ON)@T J D Typical RJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 50oC/W when mounted on a 1 in2 pad of 2oz copper. b. 105oC/W when mounted on a 0.04 in2 pad of 2oz copper. c. 125oC/W when mounted on a 0.006 in2 pad of 2oz copper. 1a 1b 1c Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%. NDS8426A Rev.B1 Typical Electrical Characteristics 40 ID , DRAIN-SOURCE CURRENT (A) 1.8 VGS =4.5V 3.5 2.7 R DS(on), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 2.5 2.0 1.6 30 1.4 V GS = 2.0 V 20 1.5 1.2 2.5 2.7 3.0 3.5 10 1 4.5 0 0 0.5 1 1.5 2 0.8 0 8 V DS , DRAIN-SOURCE VOLTAGE (V) 16 24 I D , DRAIN CURRENT (A) 32 40 Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.6 1.8 I D = 10.5A DRAIN-SOURCE ON-RESISTANCE VGS =4.5V 1.6 1.4 1.2 1 0.8 0.6 0.4 DRAIN-SOURCE ON-RESISTANCE 1.4 R DS(ON), NORMALIZED 1.2 R DS(on), NORMALIZED V GS = 4.5V TJ = 125C 25C 1 0.8 -55C 0.6 -50 -25 0 25 50 75 100 T , JUNCTION TEMPERATURE (C) J 125 150 0 10 20 I D , DRAIN CURRENT (A) 30 40 Figure 3. On-Resistance Variation with Temperature. Figure 4. On-Resistance Variation with Drain Current and Temperature. 40 GATE-SOURCE THRESHOLD VOLTAGE V DS = 5V 32 T J = -55C 125 1.3 25 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 -50 -25 VDS = VGS I D = 250A I D, DRAIN CURRENT (A) 24 16 8 0 0 0.5 1 1.5 2 V GS , GATE TO SOURCE VOLTAGE (V) 2.5 V GS(th) , NORMALIZED 0 25 50 75 100 T , JUNCTION TEMPERATURE (C) J 125 150 Figure 5. Transfer Characteristics. Figure 6. Gate Threshold Variation with Temperature. NDS8426A Rev.B1 Typical Electrical Characteristics (continued) 1.12 30 DRAIN-SOURCE BREAKDOWN VOLTAGE 1.08 I S , REVERSE DRAIN CURRENT (A) I D = 250A 10 VGS = 0V TJ = 125C 25C BV DSS , NORMALIZED 1 1.04 0.1 -55C 1 0.01 0.96 0.001 0.92 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (C) 125 150 0.0001 0 0.3 0.6 0.9 V SD , BODY DIODE FORWARD VOLTAGE (V) 1.2 Figure 7. Breakdown Voltage Variation with Temperature. Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature. 5000 3000 2000 CAPACITANCE (pF) V GS , GATE-SOURCE VOLTAGE (V) 4 I D = 10.5A Ciss 3 V DS = 5V 10V 15V 1000 Coss 2 500 200 f = 1 MHz V GS = 0 V 0 .2 0 .5 1 2 5 V , DRAIN TO SOURCE VOLTAGE (V) DS 1 Crss 10 15 20 100 0 .1 0 0 8 16 24 Q g , GATE CHARGE (nC) 32 40 Figure 9. Capacitance Characteristics. Figure 10. Gate Charge Characteristics. VDD V IN D t on t off tr 90% RL V OUT t d(on) t d(off) 90% tf VGS R GEN VOUT G DUT 10% 10% INVERTED 90% S V IN 10% 50% 50% PULSE WIDTH Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms. NDS8426A Rev.B1 Typical Electrical and Thermal Characteristics (continued) 2.5 DS , TRANSCONDUCTANCE (SIEMENS) 80 STEADY-STATE POWER DISSIPATION (W) V 60 = 5V T J = -55C 1a 2 25C 40 125C 1.5 1b 1c 20 1 4.5"x5" FR-4 Board TA = 2 5 C Still Air o g FS 0 0.5 0 6 12 18 24 30 0 I D , DRAIN CURRENT (A) 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 1 Figure 13. Transconductance Variation with Drain Current and Temperature. Figure 14. SO-8 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. 11 1a 60 30 RD S(O N) LIM IT 10 1m 10 ms s , STEADY-STATE DRAIN CURRENT (A) 0 s 10 I , DRAIN CURRENT (A) 10 5 9 10 1s 0m s 8 1b 1c 4.5"x5" FR-4 Board 1 0.5 V GS = 4.5V SINGLE PULSE R J A = See Note 1c T A = 25C A 10 s DC 7 TA = 2 5 C Still Air VG S = 4 . 5 V o D I D 0.1 1 0.05 0.1 6 0 0 .2 0 .4 0 .6 0 .8 2oz COPPER MOUNTING PAD AREA (in 2 ) 0.2 0.5 1 3 5 10 V , DRAIN-SOURCE VOLTAGE (V) DS 20 40 Figure 15. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. Figure 16. Maximum Safe Operating Area. 1 0 .5 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.05 0.02 0.01 Single Pulse P(pk) 0 .2 0 .1 0 .0 5 0 .0 2 0 .0 1 0 .0 0 5 0 .0 0 2 0 .0 0 1 0 .0001 R JA (t) = r(t) * R JA R JA = See Note 1c t1 TJ - T t2 = P * R JA (t) A Duty Cycle, D = t 1 / t 2 0 .001 0 .0 1 0 .1 1 10 100 300 t 1 , TIME (sec) Figure 17. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. NDS8426A Rev.B1 SO-8 Tape and Reel Data and Package Dimensions SOIC(8lds) Packaging Configuration: Figure 1.0 Packaging Description: EL ECT ROST AT IC SEN SIT IVE DEVICES DO NO T SHI P OR STO RE N EAR ST RO NG EL ECT ROST AT IC EL ECT RO M AGN ETI C, M AG NET IC O R R ADIO ACT IVE FI ELD S TNR D ATE PT NUMB ER PEEL STREN GTH MIN ___ __ ____ __ ___gms MAX ___ ___ ___ ___ _ gms Antistatic Cover Tape ESD Label SOIC-8 parts are shipped in tape. The carrier tape is made from a dissipative (carbon filled) polycarbonate resin. The cover tape is a multilayer film (Heat Activated Adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. These reeled parts in standard option are shipped with 2,500 units per 13" or 330cm diameter reel. The reels are dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 500 units per 7" or 177cm diameter reel. This and some other options are further described in the Packaging Information table. These full reels are individually barcode labeled and placed inside a standard intermediate box (illustrated in figure 1.0) made of recyclable corrugated brown paper. One box contains two reels maximum. And these boxes are placed inside a barcode labeled shipping box which comes in different sizes depending on the number of parts shipped. Static Dissipative Embossed Carrier Tape F63TNR Label Customized Label F852 NDS 9959 F852 NDS 9959 F852 NDS 9959 F852 NDS 9959 SOIC (8lds) Packaging Information Packaging Option Packaging type Qty per Reel/Tube/Bag Reel Size Box Dimension (mm) Max qty per Box Weight per unit (gm) Weight per Reel (kg) Note/Comments Standard (no flow code) TNR 2,500 13" Dia 343x64x343 5,000 0.0774 0.6060 L86Z Rail/Tube 95 530x130x83 30,000 0.0774 F011 TNR 4,000 13" Dia 343x64x343 8,000 0.0774 0.9696 D84Z TNR 500 7" Dia 184x187x47 1,000 0.0774 0.1182 F852 NDS 9959 Pin 1 SOIC-8 Unit Orientation 343mm x 342mm x 64mm Standard Intermediate box ESD Label F63TNR Label sample LOT: CBVK741B019 FSID: FDS9953A QTY: 2500 SPEC: F63TNLabel F63TN Label ESD Label (F63TNR)3 D/C1: D9842 D/C2: QTY1: QTY2: SPEC REV: CPN: N/F: F SOIC(8lds) Tape Leader and Trailer Configuration: Figure 2.0 Carrier Tape Cover Tape Components Trailer Tape 640mm minimum or 80 empty pockets Leader Tape 1680mm minimum or 210 empty pockets July 1999, Rev. B SO-8 Tape and Reel Data and Package Dimensions, continued SOIC(8lds) Embossed Carrier Tape Configuration: Figure 3.0 T E1 P0 D0 F K0 Wc B0 E2 W Tc A0 P1 D1 User Direction of Feed Dimensions are in millimeter Pkg type SOIC(8lds) (12mm) A0 6.50 +/-0.10 B0 5.30 +/-0.10 W 12.0 +/-0.3 D0 1.55 +/-0.05 D1 1.60 +/-0.10 E1 1.75 +/-0.10 E2 10.25 min F 5.50 +/-0.05 P1 8.0 +/-0.1 P0 4.0 +/-0.1 K0 2.1 +/-0.10 T 0.450 +/0.150 Wc 9.2 +/-0.3 Tc 0.06 +/-0.02 Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481 rotational and lateral movement requirements (see sketches A, B, and C). 20 deg maximum Typical component cavity center line 0.5mm maximum B0 20 deg maximum component rotation 0.5mm maximum Sketch A (Side or Front Sectional View) Component Rotation A0 Sketch B (Top View) Typical component center line Sketch C (Top View) Component lateral movement SOIC(8lds) Reel Configuration: Figure 4.0 Component Rotation W1 Measured at Hub Dim A Max Dim A max Dim N See detail AA 7" Diameter Option B Min Dim C See detail AA W3 Dim D min 13" Diameter Option W2 max Measured at Hub DETAIL AA Dimensions are in inches and millimeters Tape Size 12mm Reel Option 7" Dia Dim A 7.00 177.8 13.00 330 Dim B 0.059 1.5 0.059 1.5 Dim C 512 +0.020/-0.008 13 +0.5/-0.2 512 +0.020/-0.008 13 +0.5/-0.2 Dim D 0.795 20.2 0.795 20.2 Dim N 2.165 55 7.00 178 Dim W1 0.488 +0.078/-0.000 12.4 +2/0 0.488 +0.078/-0.000 12.4 +2/0 Dim W2 0.724 18.4 0.724 18.4 Dim W3 (LSL-USL) 0.469 - 0.606 11.9 - 15.4 0.469 - 0.606 11.9 - 15.4 12mm 13" Dia (c) 1998 Fairchild Semiconductor Corporation July 1999, Rev. B SO-8 Tape and Reel Data and Package Dimensions, continued SOIC-8 (FS PKG Code S1) 1:1 Scale 1:1 on letter size paper Dimensions shown below are in: inches [millimeters] Part Weight per unit (gram): 0.0774 9 September 1998, Rev. A TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM CoolFETTM CROSSVOLTTM E2CMOSTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM GTOTM HiSeCTM DISCLAIMER ISOPLANARTM MICROWIRETM POPTM PowerTrenchTM QFETTM QSTM Quiet SeriesTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 TinyLogicTM UHCTM VCXTM FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. |
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