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CXP845F60
CMOS 8-bit Single Chip Microcomputer
Description The CXP845F60 is a CMOS 8-bit microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time-base timer, capture timer/counter, PWM output and the like besides the basic configurations of 8-bit CPU, flash EEPROM, RAM and I/O port. The CXP845F60 also provides a sleep/stop functions that enable to execute the power-on reset function or lower the power consumption. The CXP845F60 is the flash EEPROM-incorporated version of the CXP84540/84548 with a built-in mask ROM. This enables program writing and erasing. Thus, it is most suitable for evaluation use during system development and for small-quantity production. 80 pin QFP (Plastic)
Features * A wide instruction set (213 instructions) which covers various types of data -- 16-bit arithmetic/multiplication and division/Boolean bit operation instructions * Minimum instruction cycle 143ns at 28MHz operation (4.5 to 5.5V) * Incorporated flash EEPROM 60K bytes Rewrite time 100 times * Incorporated RAM 1472 bytes * Peripheral functions -- A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 1.93s at 28MHz) -- Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes, latch output function, MSB/LSB first selectable), 1 channel 8-bit clock sync type, 1 channel -- Timer 8-bit timer 8-bit timer/counter 19-bit time-base timer 16-bit capture time/counter -- PWM output 8 bits, 2 channels * Interruption 14 factors, 14 vectors, multi-interruption possible * Standby mode Sleep/stop * Package 80-pin plastic QFP Structure Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E96906-PS
Block Diagram
INT0 INT1 INT2 INT3
NMI
EXTAL XTAL RST VDD Vss
AVREF
AVss
PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A
AN0 to AN7
8
A/D CONVERTER
INTERRUPT CONTROLLER
SPC700 CPU CORE
CLOCK GENERATOR/ SYSTEM CONTROL
8
PA0 to PA7
8
PB0 to PB7
PWM0 PWM1
8 BIT PWM GENERATOR 0 8 BIT PWM GENERATOR 1
8
PC0 to PC7
Flash EEPROM 60K BYTES
RAM 1472 BYTES
8 4 4
PD0 to PD7 PE0 to PE3 PE4 to PE7 PF0 to PF7
CS0 SI0 SO0 SCK0 LAT0 SI1 SO1 SCK1
SERIAL INTERFACE UNIT 0
PWE TETA TETB TETC
-2-
FIFO
SERIAL INTERFACE UNIT 1
PRESCALER/ TIME-BASE TIMER
8
8
PG0 to PG7
EC0
8 BIT TIMER/COUNTER 0 8 BIT TIMER 1 2
8
PH0 to PH7
TO CINT EC1
16 BIT CAPTURE TIMER/COUNTER 2 2
8
PI0 to PI7
CXP845F60
CXP845F60
Pin Assignment 1 (Top View)
PWE
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PF2
PF1
PF0
VDD
PG0
PI7
PI6
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PF3 PF4 PF5 PF6 PF7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0 PH1 PH2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PI4 PI3/INT3 PI2/INT2 PI1/INT1 PI0/INT0 PE5/TO/PWM1/(TETA) PE4/PWM0/(TETB) PE3/NMI/(TETC) PE2/CINT PE1/EC1 PE0/EC0 PB7/SO1 PB6/SI1 PB5/SCK1 PB4/SO0 PB3/SI0 PB2/SCK0 PB1/CS0 PB0/LAT0 PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3
VSS
PE6
PE7
AVSS
AVREF
PA0/AN0
PA1/AN1
PH3
Notes) 1. PWE (Pin 73) is left open during normal operation. 2. See the Appendix concerning the Pins 57 to 59 (TETA, TETB and TETC).
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PA2/AN2
PH4
PH5
PH6
PH7
RST
EXTAL
XTAL
PI5
CXP845F60
Pin Description Symbol I/O (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of the pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Description
PA0/AN0 to PA7/AN7
I/O/Analog input
Analog inputs to A/D converter. (8 pins)
PB0/LAT0 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1
I/O/Output I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins)
Latch output for serial interface (CH0). Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sink current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) External event inputs for timer/counter. (2 pins) Capture trigger input. (Port E) 8-bit port. Lower 4 bits are for inputs; upper 4 bits are for outputs. (8 pins) Non-maskable interruption request input. 8-bit PWM0 output. Rectangular wave output for 16-bit timer/counter and 8-bit PWM1 output. Control pins for flash EEPROM write. (3 pins)
PC0 to PC7
I/O
PD0 to PD7
I/O
PE0/EC0 PE1/EC1 PE2/CINT PE3/NMI/ (TETC) PE4/PWM0/ (TETB)
Input/Input Input/Input Input/Input Input/Input/ (Input) Output/Output/ (Input)
Output/Output/ PE5/TO/ PWM1/(TETA) Output/(Input) PE6 PE7 Output Output
PF0 to PF7
I/O
(Port F) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins)
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CXP845F60
Symbol
I/O
Description (Port G) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) (Port H) 8-bit I/O port. I/O and standby release input function can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port I) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) External interruption request inputs. (4 pins)
PG0 to PG7
I/O
PH0 to PH7
I/O
PI0/INT0 to PI3/INT3 PI4 to PI7 EXTAL XTAL RST
I/O/Input I/O Input Output I/O
Connects a crystal for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. System reset for active at Low level. This pin is I/O pin, and outputs Low level at the power on with the power-on reset function executed. Flash EEPROM write enable pin. Write is enabled at Low level; write is prohibited at High level. Leave this pin open for normally operation. Reference voltage input for A/D converter. A/D converter GND. Positive power supply. GND
PWE AVREF AVss VDD Vss
Input Input
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CXP845F60
Input/Output Circuit Formats for Pins Pin Port A
Pull-up resistor "0" when reset Port A data
Circuit format
When reset
PA0/AN0 to PA7/AN7
Data bus
Port A direction "0" when reset
IP
Input protection circuit
Hi-Z
RD (Port A) Port A function selection "0" when reset A/D converter
Input multiplexer Pull-up transistor Approx. 100k (VDD = 4.5 to 5.5V)
8 pins Port B
Pull-up resistor "0" when reset LAT0 Latch output enable
PB0/LAT0
Port B data IP Port B direction "0" when reset Data bus RD (Port B) Pull-up transistor Approx. 100k (VDD = 4.5 to 5.5V)
Hi-Z
1 pin Port B
Pull-up resistor "0" when reset Port B data
PB1/CS0 PB3/SI0 PB6/SI1
Port B direction "0" when reset Data bus RD (Port B) CS0 SI0 SI1 Schmitt input
Hi-Z
IP
3 pins
Pull-up transistor Approx. 100k (VDD = 4.5 to 5.5V)
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CXP845F60
Pin Port B
Pull-up resistor "0" when reset SCK OUT Serial clock output enable Port B function selection "0" when reset Port B data Port B direction "0" when reset
Circuit format
When reset
PB2/SCK0 PB5/SCK1
IP
Hi-Z
Data bus RD (Port B)
Schmitt input
2 pins Port B
SCK0, SCK1 in
Pull-up transistor Approx. 100k (VDD = 4.5 to 5.5V)
Pull-up resistor SO Serial data output enable Port B function selection
PB4/SO0 PB7/SO1
"0" when reset Port B data Port B direction "0" when reset Data bus RD (Port B) Pull-up transistor Approx. 100k (VDD = 4.5 to 5.5V) IP
Hi-Z
2 pins Port C
Pull-up resistor "0" when reset Port C data
2
PC0 to PC7
Port C direction "0" when reset Data bus RD (Port C) 1 Large current drive 12mA (VDD = 4.5 to 5.5V) 2 Pull-up transistor *1 IP
Hi-Z
8 pins -7-
Approx. 100k (VDD = 4.5 to 5.5V)
CXP845F60
Pin Port E PE0/EC0 PE1/EC1 PE2/CINT PE3/NMI/ (TETC) 4 pins Port E
Schmitt input IP
Circuit format
When reset
EC0, EC1 CINT, NMI (to flash EEPROM circuit) Data bus RD (Port E)
Hi-Z
PWM0 Port E function selection "0" when reset Port E data "1" when reset
PE4/PWM0/ (TETB)
High level
1 pin Port E
Data bus RD (Port E) (to flash EEPROM circuit)
Internal reset signal Port E data 00 MPX 01 1x
PE5/TO/ PWM1/ (TETA)
"1" when reset TO PWM1
Port E function selection (upper) Port E function selection (lower) "00" when reset TO output enable (to flash EEPROM circuit) Pull-up transistor Approx. 150k (VDD = 4.5 to 5.5V)
High level High level at ON resistance of pull-up transistor during a reset.
1 pin Port E
PE6, PE7
Port E data "0" when reset
Low level
Data bus
2 pins
RD (Port E)
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CXP845F60
Pin Port D Port F Port G PD0 to PD7 PF0 to PF7 PG0 to PG7 PI4 to PI7 Port I
Pull-up resistor "0" when reset
Circuit format
When reset
Ports D, F, G, I data
Ports D, F, G, I direction "0" when reset Data bus RD
IP
Hi-Z
28 pins Port H
Pull-up transistor Approx. 100k (VDD = 4.5 to 5.5V)
Pull-up resistor "0" when reset Port H data
PH0 to PH7
Port H direction "0" when reset Data bus RD (Port H) Standby release Edge detection Pull-up transistor Approx. 100k (VDD = 4.5 to 5.5V) IP
Hi-Z
8 pins Port I
Pull-up resistor "0" when reset Port I data
PI0/INT0 to PI3/INT3
Data bus
Port I direction "0" when reset Schmitt input RD INT0 INT1 INT2 INT3
IP
Hi-Z
4 pins -9-
Pull-up transistor Approx. 100k (VDD = 4.5 to 5.5V)
CXP845F60
Pin
Circuit format
When reset
EXTAL XTAL
* Diagram shows the circuit composition during oscillation. EXTAL IP IP * Feedback resistor is removed during stop mode and XTAL becomes High level.
Oscillation
2 pins
XTAL
Pull-up resistor
RST
IP
Schmitt input
Low level
from power-on reset circuit
1 pin
Pull-up resistor
PWE High level
IP to flash EEPROM circuit
1 pin
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CXP845F60
Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage High level output current High level total output current Low level output current IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation IOL Topr Tstg PD Symbol VDD AVSS VIN VOUT IOH IOH IOL Ratings -0.3 to +7.0 -0.3 to +0.3 -0.3 to +7.01 -0.3 to +7.01 -5 -50 15 20 100 -20 to +75 -55 to +150 600 Unit V V V V mA mA mA mA mA C C mW Output (value per pin)
(Vss = 0V reference) Remarks
Total for all output pins All pins excluding large current outputs (value per pin) Large current outputs (value per pin2) Total for all output pins
1 VIN and VOUT must not exceed VDD + 0.3V. 2 The large current drive transistor is the N-ch transistor of Port C (PC). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI.
Recommended Operating Conditions Item Symbol Min. 4.5 Supply voltage VDD 3.5 2.0 VIH High level input voltage VIHS VIHEX VIL Low level input voltage Operating temperature VILS VILEX Topr 0.7VDD 0.8VDD Max. 5.5 5.5 5.5 VDD VDD V V V V V V C V Unit
(Vss = 0V reference) Remarks Guaranteed operation range for 1/2 and 1/4 frequency dividing modes Guaranteed operation range for 1/16 frequency dividing and sleep modes Guaranteed data hold range during stop mode 1 Hysteresis input2 EXTAL3 1 Hysteresis input2 EXTAL3
VDD - 0.4 VDD + 0.3 0 0 -0.3 -20 0.3VDD 0.2VDD +0.4 +75
1 Normal input ports (PA, PB0, PB4, PB7, PC, PE0 to PE3, PD, PF to PH, PI4 to PI7) 2 RST, CINT, CS0, SCK0, SCK1, EC0, EC1, SI0, SI1, NMI, INT0, INT1, INT2, INT3 3 Specifies only during external clock input. - 11 -
CXP845F60
Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V) Item High level output voltage Low level output voltage Symbol VOH Pin PA to PD, PE4 to PE7, PF to PI, RST (only VOL) PC IIHE IILE Input current IILR IIL I/O leakage current RST PA to PD1 PF to PI1 PA to PD1 PF to PI1 PE0 to PE3 EXTAL Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 4.0V VDD = 4.5V, VIL = 4.0V VDD = 5.5V, VI = 0, 5.5V For 1/2 frequency dividing mode VDD = 5.5V, 28MHz crystal oscillation (C1 = C2 = 1pF) Sleep mode VDD IDDS2 VDD = 5.5V, 28MHz crystal oscillation (C1 = C2 = 1pF) Stop mode IDDS3 PA to PD, PE0 to PE3, PF to PI, EXTAL, RST VDD = 5.5V, termination of 28MHz crystal oscillation Clock 1MHz 0V for all pins excluding measured pins 30 A 2.5 10 mA 38 66 mA -2.78 10 0.1 -0.1 -1.5 (Ta = -20 to +75C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 25 -25 -400 -50 Typ. Max. Unit V V V V V A A A A A A
VOL
IIZ IDD1 IDD2
Supply current 2
IDDS1
Input capacity
CIN
10
20
pF
1 For PA to PD and PF to PI pins, specifies the input current when pull-up resistance is selected; leakage current when no resistance is selected. 2 When all output pins are left open.
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CXP845F60
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time 1 Symbol fC Pin (Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Min. 1 15.6 100 Typ. Max. Unit 28 MHz ns ns ns 20 ms
XTAL Fig. 1, Fig. 2 EXTAL EXTAL EXTAL EC0 EC1 EC0 EC1 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3
tXL, tXH tCR, tCF tEH, tEL tER, tEF
tsys + 501
tsys indicates the three values according to the contents of the clock control register (CLC: 00FEh) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
1/fc
VDD - 0.4V EXTAL 0.4V
tXH
tCF
tXL
tCR
Fig. 1. Clock timing
Crystal oscillation Ceramic oscillation
External clock
EXTAL
XTAL
EXTAL
XTAL
C1
C2
74HC04
Fig. 2. Clock applied conditions
0.8VDD EC0 EC1 0.2VDD
tEH tTH
tEF tTF
tEL tTL
tER tTR
Fig. 3. Event count clock timing - 13 -
CXP845F60
(2) Serial transfer (CH0) Item CS0 SCK0 delay time CS0 SCK0 float delay time CS0 SO0 delay time CS0 SO0 float delay time CS0 High level width SCK0 cycle time SCK0 High, Low level width SI0 input setup time (for SCK0 ) SI0 input hold time (for SCK0 ) SCK0 SO0 delay time SCK0 LAT0 output delay time LAT0 data pulse width Symbol Pin SCK0
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode Latch output mode (SCK0 = output mode) Latch output mode (SCK0 = output mode) Min. Max. 1.5tsys + 100 1.5tsys + 100 1.5tsys + 100 1.5tsys + 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tDCSK
tDCSKF SCK0 tDCSO SO0 tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
SCK0
tsys + 150
2tsys + 200 8000/fc
SCK0
tsys + 90
4000/fc - 25 50 100
SI0
SI0
tsys + 100
50
SO0
tsys + 100
50
ns ns ns ns
tLADLY LAT0 tLAPLS LAT0
tKCY tKCY - 10
tKCY + 50 tKCY + 50
Note 1) tsys indicates the three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
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CXP845F60
tWHCS
0.8VDD CS0 0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Output data 0.2VDD
tLADLY
tLAPLS
0.8VDD
0.8VDD
LAT0
Fig. 4. Serial transfer CH0 timing
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CXP845F60
(3) Serial transfer (CH1) Item SCK1 cycle time SCK1 High, Low level width SI1 input setup time (for SCK1 ) SI1 input hold time (for SCK1 ) SCK1 SO1 delay time Symbol Pin SCK1
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, VSS = 0V reference) Conditions Input mode Output mode Input mode Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode Min. 500 8000/fc 200 4000/fc - 25 50 100 100 50 100 50 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
SCK1
SI1
SI1
SO1
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
tKCY tKL tKH
0.8VDD SCK1 0.2VDD
tSIK
tKSI
0.8VDD SI1 Input data 0.2VDD
tKSO
0.8VDD SO1 0.2VDD Output data
Fig. 5. Serial transfer CH1 timing
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CXP845F60
(4) A/D converter characteristics (Ta = -20 to +75C, VDD = 4.5 to 5.5V, AVREF = 4.0 to VDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time VZT1 VFT2 Ta = 25C VDD = AVREF = 5.0V VSS = AVSS = 0V -10 4910 27/fADC3 6/fADC3 AVREF AN0 to AN7 Operation mode AVREF Sleep mode Stop mode VDD - 0.5 0 0.6 VDD AVREF 1.0 10 10 4970 Symbol Pin Conditions Min. Typ. Max. 8 4 70 5030 Unit Bits LSB mV mV s s V V mA A
tCONV tSAMP
VIAN IREF
Reference input voltage VREF Analog input voltage AVREF current IREFS
FFh FEh
Linearity error 01h 00h VZT Analog input VFT
1 VZT: Value at which the digital conversion value changes from 00H to 01H and vice versa. 2 VFT: Value at which the digital conversion value changes from FEH to FFH and vice versa. 3 fADC indicates the values below due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F9H). fADC = fc (CKS = "0"), fc/2 (CKS = "1") However, the selection for fADC = fc (CKS = "0") is limited in the clock range of fc = 1 to 14MHz (VDD = 4.5 to 5.5V).
Digital conversion value
Fig. 6. Definition of A/D converter terms
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CXP845F60
(5) Interruption, reset input Item
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin INT0 INT1 INT2 INT3 NMI RST Conditions Min. Max. Unit
External interruption High, Low level width
tIH tIL tRSL
1
s
Reset input Low level width
32/fc
s
tIH
tIL
INT0 INT1 INT2 INT3 NMI (Specifies NMI only for the falling edge.)
0.8VDD 0.2VDD tIL tIH 0.8VDD 0.2VDD
Fig 7. Interruption input timing
tRSL
RST 0.2VDD
Fig. 8. RST input timing
(6) Power-on reset Item Power supply rise time Power supply cut-off time Symbol Pin VDD
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, VSS = 0V reference) Conditions Power-on reset Repetitive power-on reset Min. 0.05 1 Max. 50 Unit ms ms
tR tOFF
4.5V VDD 0.2V 0.2V
tR Turn the power on smoothly.
tOFF
Fig. 9. Power-on reset - 18 -
CXP845F60
Appendix
(i) Main clock (ii) Main clock
EXTAL
XTAL Rd
EXTAL
XTAL Rd
C1
C2 C1 C2
Fig. 10. SPC700 Series recommended oscillation circuit Circuit example
Manufacturer
Model CSA8.00MTZ CSA10.0MTZ CSA12.00MTZ CST8.00MTW1
fc (MHz) 8.00 10.00 12.00 8.00 10.00 12.00 16.00 16.00 20.00 24.00 28.00 20.00 24.00 28.00 28.00
C1 (pF)
C2 (pF)
Rd ()
(i) 30 30 0 (ii)
MURATA MFG CO., LTD.
CST10.0MT1 CST12.0MTW1 CSA16.00MXZ040 CST16.00MXZ0C11 CSA20.00MXZ040 CSA24.00MXZ040 CSA28.00MXZ040 CCR20.0MC61
5 5 OPEN 3 3 16 16 1 1
5 5 OPEN 3 3 16 16 1 1
0 0 0 0 0 0 0 220 220
(i) (ii)
(i)
TDK CORPORATION. CCR24.0MC61 HC49/U-S KINSEKI LTD. CX-11F
(ii)
(i)
1 Models with the built-in ground capacitance (C1, C2).
Selection Guide Option item Package ROM capacitance Reset pin pull-up resistor Power-on reset circuit Mask 100-pin plastic QFP 40K bytes 48K bytes CXP845F60Q-1100-pin plastic QFP Flash EEPROM 60K bytes Existent Existent
Existent/Non-existent Existent/Non-existent
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CXP845F60
Characteristics Curves
IDD vs. VDD
(fc = 28MHz, Ta = 25C, Typical) 50 40 30 20 10 Sleep mode 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode 40
IDD vs. fc
(VDD = 5V, Ta = 25C, Typical)
1/2 dividing mode
IDD - Supply current [mA]
IDD - Supply current [mA]
1 0.5 (500A)
30 1/4 dividing mode
0.1 (100A)
20 1/16 dividing mode
0.01 (10A)
10 Stop mode Sleep mode
0 1 2 3 4 5 6 7 VDD - Supply voltage [v] 8 9 0 10 20 fc - System clock [MHz] 30
- 20 -
CXP845F60
Writing to Flash EEPROM The CXP845F60 contains the 60K bytes of flash EEPROM. There are two methods to write to the flash EEPROM; off-board write and on-board write. The on-board write supports boot mode and user programming mode. Rewriting at the room temperature is recommended. 1. Off-board write In order to execute the off-board write, the microcomputer is attached on a conversion adaptor and the adaptor is inserted in the socket of the SFP-1 (flash memory programmer) or NICE-SPC700R. (See Fig. 11.) See the operation manuals for the operation methods of the SFP-1 and NICE-SPC700R. (Mitec SYSTEMS, Inc. manufactures and sells the SFP-1 and NICE-SPC700R.)
Conversion adaptor
Flash memory programmer SFP-1
Fig. 11. Off-board write (when writing by using SFP-1) 2. On-board write This is performed with the microcomputer mounted on the board. The CXP845F60 supports boot mode and user programming mode. In boot mode, write is performed through the communication with the SFP-1 as shown in Fig. 12.
User board SIO communication cable (8 pins) CXP845F60
Flash memory programmer SFP-1
Fig. 12. On-board write boot mode In user programming mode, write is performed in microcomputer mode (normal operation mode) by the communication method (SIO, I/O, etc.) according to the user's application. See the guide of the CXP845F60 write for actual use. - 21 -
CXP845F60
When the on-board write is performed, the pins and flash mode register (FMOD: 01F4h, 0FF0h) should be set as follows. Pins Mode RST Onboard write Boot mode User programming mode High level TETA Low fixed X TETB TETC PWE FLMOD bit 11 Low fixed X X 1 X: don't care High output High fixed FMOD resister
1 FLMOD bit is set to "1" automatically in boot mode.
User circuit
Cut off the connection to other circuits during the flash EEPROM rewrite.
When normal operation GND SI SO SCK RES VIN GND Vpp VSS SO1 SI1 SCK1 RST VDD VSS SEL Switching circuit In boot mode Switched to boot mode for low level 1 Reset circuit
SO1 SI1 SCK1
VDD
Flash MCU PWE RST TETC TETB TETA When normal operation Switching circuit In boot mode VSS Switched to boot mode for low level
AMP CT receptacle AMP CT connector 173977-8 175489-8
1 The Vpp signal for the SFP-1 is pulled down with 4.7k. Connecting cable permits writing when PWE pin is fixed at low level. Also, it can be used as select signal of the switching circuit. Fig. 13. Connection example for boot mode Connector for SFP-1 (AMP CT receptacle 173977-8) Symbol GND SI SO SCK RST VIN GND Vpp 4.7k pull-up 4.7k pull-up Open drain, 4.7k pull-up Open drain, 4.7k pull-up Open drain, 4.7k pull-up Remarks Connector for user board (AMP CT connector 175489-8) Symbol GND SO1 SI1 SCK1 RST VDD GND PWE - 22 - Pull-up in the microcomputer Pull-up in the microcomputer (mask option) Remarks
Pin No. 1 2 3 4 5 6 7 8
Signal direction
CXP845F60
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 64 41 + 0.1 0.15 - 0.05 0.15
65
40
+ 0.4 14.0 - 0.1
17.9 0.4
A 80 25 + 0.2 0.1 - 0.05
0.8
0.12
M
+ 0.15 0.35 - 0.1
+ 0.35 2.75 - 0.15
0 to 10 DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.6g QFP-80P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
SONY CODE EIAJ CODE JEDEC CODE
QFP080-P-1420-A
- 23 -
0.8 0.2
1
24
16.3

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