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PRELIMINARY KM736V687 64Kx36-Bit Synchronous Burst SRAM FEATURES Synchronous Operation. On-Chip Address Counter. Write Self-Timed Cycle. On-Chip Address and Control Registers. Single 3.3V 5% Power Supply. 5V Tolerant Inputs except I/O Pins. Byte Writable Function. Global Write Enable Controls a full bus-width write. Power Down State via ZZ Signal. Asynchronous Output Enable Control. ADSP, ADSC, ADV Burst Control Pins. LBO Pin allows a choice of either a interleaved burst or a linear burst. * Three Chip Enables for simple depth expansion with No Data Contention. * TTL-Level Three-State Output. * 100-TQFP-1420A * * * * * * * * * * * * 64Kx36 Synchronous SRAM GENERAL DESCRIPTION The KM736V687 is 2,359,296 bits Synchronous Static Random Access Memory designed to support zero wait state performance for advanced Pentium/Power PC based system. And with CS1 high, ADSP is blocked to control signals. It can be organized as 64K words of 36 bits. And it integrates address and control registers, a 2-bit burst address counter and high output drive circuitry onto a single integrated circuit for reduced components counts implementation of high performance cache RAM applications. Write cycles are internally self-timed and synchronous. The self-timed write feature eliminates complex off chip write pulse shaping logic, simplifying the cache design and further reducing the component count. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the systems burst sequence and are controlled by the burst address advance(ADV) input. ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The KM736V687 is implemented with SAMSUNGs high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce. FAST ACCESS TIMES Parameter Cycle Time Clock Access Time Output Enable Access Time Symbol tCYC tCD tOE -8 12 8.5 4 -9 12 9 4 -10 Unit 15 10 5 ns ns ns LOGIC BLOCK DIAGRAM CLK LBO CONTROL REGISTER ADV ADSC BURST CONTROL LOGIC BURST ADDRESS COUNTER A0~A1 64Kx36 MEMORY ARRAY A0~A1 ADDRESS REGISTER A2~A15 ADSP A0~A15 CS1 CS2 CS2 GW BW WEa WEb WEc WEd OE ZZ DQa0 ~ DQd7 DQPa ~ DQPd DATA-IN REGISTER CONTROL REGISTER CONTROL LOGIC OUTPUT BUFFER -2- May 1997 Rev 1.0 PRELIMINARY KM736V687 PIN CONFIGURATION(TOP VIEW) ADSC ADSP WEd WEb WEa WEc ADV 83 CLK CS1 CS2 CS2 VDD GW VSS BW OE A6 A7 A8 82 A9 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 64Kx36 Synchronous SRAM 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 VSS VDD A5 A4 A3 A2 A1 A0 A10 A11 A12 A13 A14 LBO N.C. N.C. N.C. N.C. A15 PIN NAME SYMBOL A0 - A15 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37, 44,45,46,47,48,49, 81,82,99,100 83 84 85 89 98 97 92 93,94,95,96 86 88 87 64 31 SYMBOL VDD VSS N.C. DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~Pd VDDQ VSSQ PIN NAME Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs TQFP PIN NO. 15,41,65,91 17,40,67,90 14,16,38,39,42,43,50,66 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 ADV ADSP ADSC CLK CS1 CS2 CS2 WEx OE GW BW ZZ LBO Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control Output Power Supply (+3.3V) Output Ground N.C. 50 DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 N.C. VDD N.C. VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 Pin TQFP (20mm x 14mm) DQPb DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS N.C. VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa -3- May 1997 Rev 1.0 PRELIMINARY KM736V687 FUNCTION DESCRIPTION The KM736V687 is a synchronous SRAM designed to support the burst address accessing sequence of the Pentium and Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins. When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up time. ZZ pin is pulled down internally. Read cycles are initiated with ADSP(or ADSC) using the new external address clocked into the on-chip address register when both GW and BW are high or when BW is low and WEa, WEb, WEc, and WEd are high. When ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. the data of cell array accessed by the current address are projected to the output pins. Write cycles are also initiated with ADSP(or ADSC) and are differentiated into two kinds of operations; All byte write operation and individual byte write operation. All byte write occurs by enabling GW(independent of BW and WEx.), and individual byte write is performed only when GW is high and BW is low. In KM736V687, a 64Kx36 organization, WEa controls DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and DQPb, WEc controls DQc0 ~ DQc7 and DQPc and WEd controls DQd0 ~ DQd7 and DQPd. CS1 is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded. ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address increases internally for the next access of the burst when ADV is sampled low. Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is Low, linear burst sequence is selected. And this pin is High, Interleaved burst sequence is selected. 64Kx36 Synchronous SRAM BURST SEQUENCE TABLE LBO PIN HIGH First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 0 1 1 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3 A0 0 1 0 1 (Interleaved Burst) Case 4 A1 1 1 0 0 A0 1 0 1 0 Fourth Address BURST SEQUENCE TABLE LBO PIN LOW First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 1 1 0 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3 A0 0 1 0 1 A1 1 0 0 1 (Linear Burst) Case 4 A0 1 0 1 0 Fourth Address NOTE : 1. LBO pin must be tied to high or low, and floating state must not be allowed. ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2): Operation Sleep Mode Read Write Deselected ZZ H L L L L OE X L H X X I/O Status High-Z DQ High-Z Din, High-Z High-Z NOTE 1. X means "Dont Care". 2. ZZ pin is pulled down internally 3. For write cycles that following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 4. Sleep Mode means power down state of which stand-by current does not depend on cycle time. 5. Deselected means power down state of which stand-by current depends on cycle time. -4- May 1997 Rev 1.0 PRELIMINARY KM736V687 SYNCHRONOUS TRUTH TABLE CS1 H L L L L L L L X H X H X H X H CS2 X L X L X H H H X X X X X X X X CS2 X X H X H L L L X X X X X X X X ADSP X L L X X L H H H X H X H X H X ADSC L X X L L X L L H H H H H H H H ADV X X X X X X X X L L L L H H H H WRITE X X X X X X L H H H L L H H L L CLK Address Accessed N/A N/A N/A N/A N/A External Address External Address External Address Next Address Next Address Next Address Next Address Current Address Current Address Current Address Current Address Operation Not Selected Not Selected Not Selected Not Selected Not Selected Begin Burst Read Cycle Begin Burst Write Cycle Begin Burst Read Cycle Continue Burst Read Cycle Continue Burst Read Cycle Continue Burst Write Cycle Continue Burst Write Cycle Suspend Burst Read Cycle Suspend Burst Read Cycle Suspend Burst Write Cycle Suspend Burst Write Cycle 64Kx36 Synchronous SRAM NOTE : 1. X means "Dont Care". 2. The rising edge of clock is symbolized by . 3. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 4. Operation finally depends on status of asynchronous input pins(ZZ and OE). WRITE TRUTH TABLE GW H H H H H H L BW H L L L L L X WEa X H L H H L X WEb X H H L H L X WEc X H H H L L X WEd X H H H L L X Operation READ READ WRITE BYTE a WRITE BYTE b WRITE BYTE c and d WRITE ALL BYTEs WRITE ALL BYTEs NOTE : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(). ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on VDD Supply Relative to VSS Voltage on VDDQ Supply Relative to VSS Voltage on Input Pin Relative to VSS Voltage on I/O Pin Relative to VSS Power Dissipation Storage Temperature Operating Temperature Storage Temperature Range Under Bias Symbol VDD VDDQ VIN VIO PD TSTG TOPR TBIAS Rating -0.3 to 4.6 VDD -0.3 to 6.0 -0.3 to VDDQ+0.5 1.2 -65 to 150 0 to 70 -10 to 85 Unit V V V V W C C C *NOTE : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. -5- May 1997 Rev 1.0 PRELIMINARY KM736V687 OPERATING CONDITIONS(0C TA70C) Parameter Supply Voltage Ground Symbol VDD VDDQ VSS Min 3.13 3.13 0 Typ. 3.3 3.3 0 Max 3.47 3.47 0 Unit V V V 64Kx36 Synchronous SRAM CAPACITANCE*(TA=25C, f=1MHz) Parameter Input Capacitance Output Capacitance *NOTE : Sampled not 100% tested. Symbol CIN COUT Test Condition VIN=0V VOUT=0V Min - Max 5 8 Unit pF pF TEST CONDITIONS(TA=0 to 70C, VDD=3.3V5%, unless otherwise specified) Parameter Input Pulse Level Input Rise and Fall Time(Measured at 0.3V and 2.7V) Input and Output Timing Reference Levels Output Load Value 0 to 3V 2ns 1.5V See Fig. 1 DC ELECTRICAL CHARACTERISTICS(TA=0 to 70C, VDD=3.3V5%) Parameter Input Leakage Current(except ZZ) Output Leakage Current Symbol IIL IOL Test Conditions VDD=Max , VIN=VSS to VDD Output Disabled, VOUT=VSS to VDDQ Device Selected, IOUT=0mA, ZZVIL, Operating Current ICC All Inputs=VIL or VIH Cycle TimetCYC min Device deselected, IOUT=0mA, ZZVIL, f=Max, All Inputs0.2V orVDD-0.2V Device deselected, IOUT=0mA, ZZ0.2V, f=0, All Inputs=fixed (VDD-0.2V or 0.2V) Device deselected, IOUT=0mA, ZZVDD-0.2V, f=Max, All InputsVIL orVIH IOL = 8.0mA IOH = -4.0mA -8 -9 -10 -8 -9 -10 Min -2 -2 Max +2 +2 330 330 300 80 80 60 10 mA mA mA Unit A A ISB Standby Current ISB1 ISB2 Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage * VIL(Min)=-3.0(Pulse Width20ns) ** In Case of I/O Pins, the Max. VIH=VDDQ+0.5V 2.4 -0.5* 2.2 10 0.4 0.8 5.5** mA V V V V VOL VOH VIL VIH -6- May 1997 Rev 1.0 PRELIMINARY KM736V687 Output Load(A) 64Kx36 Synchronous SRAM Output Load(B) (for tLZC, tLZOE, tHZOE & tHZC) +3.3V RL=50 Dout VL=1.5V Z0=50 30pF* Dout 353 319 5pF* * Capacitive Load consists of all components of the test environment. * Including Scope and Jig Capacitance Fig. 1 AC TIMING CHARACTERISTICS(TA=0 to 70C, VDD=3.3V5%) Parameter Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width Clock Low Pulse Width Address Setup to Clock High Address Status Setup to Clock High Data Setup to Clock High Write Setup to Clock High Address/Advance Setup to Clock High Chip Select Setup to Clock High Address Hold from Clock High Address Status Hold from Clock High Data Hold from Clock High Write Hold from Clock High Address Advance Hold from Clock High Chip Select Hold from Clock High ZZ High to Power Down ZZ Low to Power Up Symbol tCYC tCD tOE tLZC tOH tLZOE tHZOE tHZC tCH tCL tAS tSS tDS tWS tADVS tCSS tAH tSH tDH tWH tADVH tCSH tPDS tPUS KM736V687-8 Min 12 4 3 0 2 4 4 2.5 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 2 2 Max 8.5 4 5 5 KM736V687-9 Min 12 4 3 0 2 4 4 2.5 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 2 2 Max 9 4 5 5 KM736V687-10 Min 15 6 3 0 2 5 5 2.5 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 2 2 Max 10 5 5 6 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cycle cycle NOTE : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state. -7- May 1997 Rev 1.0 TIMING WAVEFORM OF READ CYCLE tCH tCL CLOCK tSH tCYC KM736V687 tSS ADSP tSS tSH ADSC tAH A2 tWS tWH A3 BURST CONTINUED WITH NEW BASE ADDRESS tAS ADDRESS A1 -8tCSH tADVS tADVH (ADV INSERTS WAIT STATE) WRITE tCSS CS ADV OE tOE tHZOE tCD tOH Q2-1 Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 Q1-1 tHZC Q3-4 tLZOE Data Out Dont Care Undefined 64Kx36 Synchronous SRAM PRELIMINARY May 1997 Rev 1.0 NOTES : WRITE = L means GW = L, or GW = H, BW = L, WEx.= L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L TIMING WAVEFORM OF WRTE CYCLE tCH tCL CLOCK tSH tCYC KM736V687 tSS ADSP tSS tSH ADSC tAH A1 A2 (ADSC EXTENDED BURST) tAS ADDRESS A3 tWS tWH WRITE tCSH -9(ADV SUSPENDS BURST) tCSS CS tADVS tADVH ADV OE tDS D1-1 tLZOE Q3-4 Dont Care Undefined tDH D2-2 D2-2 D2-3 D2-4 D3-1 D3-2 D3-3 D3-4 Data In D2-1 64Kx36 Synchronous SRAM PRELIMINARY May 1997 Rev 1.0 Data Out Q0-3 TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED, ADSC=HIGH) tCH tCL CLOCK tSS tSH tCYC KM736V687 ADSP tAS tAH A2 A3 tWS tWH A1 ADDRESS WRITE - 10 tADVS tADVH tDS D2-1 tOE tHZOE tLZOE Q1-1 Q3-1 tCD tLZC tDH CS ADV OE Data In tHZC tOH Q3-2 Q3-3 Q3-4 Data Out Dont Care Undefined 64Kx36 Synchronous SRAM PRELIMINARY May 1997 Rev 1.0 TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED, ADSP=HIGH) tCH tCL CLOCK tSH tCYC KM736V687 tSS ADSC tWS A2 tWS tWH A3 A4 A5 A6 A7 A8 tWH A9 ADDRESS A1 WRITE tCSH tCSS - 11 tOE tHZOE Q1-1 Q2-1 Q3-1 Q4-1 tDS D5-1 D6-1 CS ADV OE tCD Q8-1 tDH D7-1 tOH Q9-1 tLZOE Data Out Data In 64Kx36 Synchronous SRAM Dont Care Undefined PRELIMINARY May 1997 Rev 1.0 TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSP CONTROLLED, ADSC=HIGH) tCH tCL CLOCK tCYC KM736V687 tSS tSH ADSP tAS A2 A3 A4 A5 A6 A7 A8 tAH A9 ADDRESS A1 WRITE tCSS tCSH - 12 tHZOE Q1-1 Q2-1 Q3-1 Q4-1 tDS D5-1 D6-1 tDH CS ADV OE tCD Q8-1 tOH Q9-1 tOE tLZOE Data Out Data In D7-1 Dont Care Undefined 64Kx36 Synchronous SRAM PRELIMINARY May 1997 Rev 1.0 TIMING WAVEFORM OF POWER DOWN CYCLE tCH tCL CLOCK tSH tCYC KM736V687 tSS ADSP ADSC tAH A2 tWS tWH tAS ADDRESS A1 WRITE tCSH tCSS - 13 tOE tHZC Q1-1 tPDS ZZ Setup Cycle Sleep State CS ADV OE tLZOE tHZOE Data In D2-1 D2-2 Data Out tPUS ZZ Recovery Cycle Normal Operation Mode ZZ Dont Care Undefined 64Kx36 Synchronous SRAM PRELIMINARY May 1997 Rev 1.0 PRELIMINARY KM736V687 APPLICATION INFORMATION DEPTH EXPANSION The Samsung 64Kx36 Synchronous Burst SRAM has two additional chip selects for simple depth expansion. 64Kx36 Synchronous SRAM This permits easy secondary cache upgrades from 64K depth to 128K depth without extra logic. Data Address A[0:16] A[16] A[0:15] A[16] A[0:15] I/O[0:71] CLK Address CS2 Data Address CS2 CS2 Data 64-bits Microprocessor Address CLK Cache Controller CS2 CLK ADSC WEx (Bank 0) OE CS1 ADV ADSP 64Kx36 SB SRAM CLK ADSC WEx 64Kx36 SB SRAM (Bank 1) OE CS1 ADV ADSP ADS * Please refer to attached timing diagram 1 INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) CLOCK tSS tSH ADSP tAS tAH A2 tWS tWH ADDRESS [0:n] WRITE A1 tCSS tCSH CS1 Bank 0 is selected by CS2, and Bank 1 deselected by CS2 An+1 tADVS tADVH Bank 0 is deselected by CS2, and Bank 1 selected by CS2 ADV OE tOE tHZC Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC Q2-1 Q2-2 Q2-3 Q2-4 Dont Care Undefined Data Out (Bank 0) Data Out (Bank 1) tLZOE *NOTES n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth - 14 - May 1997 Rev 1.0 PRELIMINARY KM736V687 PACKAGE DIMENSIONS 100-TQFP-1420A 22.00 0.30 20.00 0.20 64Kx36 Synchronous SRAM Units:millimeters/inches 0~8 0.127 + 0.10 - 0.05 16.00 0.30 14.00 0.20 0.10 MAX (0.83) 0.50 0.10 #1 0.65 0.30 0.10 0.10 MAX (0.58) 1.40 0.10 1.60 MAX 0.50 0.10 0.05 MIN - 15 - May 1997 Rev 1.0 |
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