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CXP84332M/84340M
CMOS 8-bit Single Chip Microcomputer
Description CXP84332M/84340M is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, capture timer/counter, remote control reception circuit, PWM output, and 32kHz timer/counter besides the basic configurations of 8-bit CPU, ROM, RAM, and I/O port. The CXP84332M/84340M also provides a sleep/stop function that enables lower power consumption. 80 pin QFP (Plastic)
Features * Wide-range instruction system (213 instructions) to cover various types of data -- 16-bit arithmetic/multiplication and division/boolean bit operation instructions * Minimum instruction cycle 200ns at 20MHz operation 122s at 32kHz operation * Incorporated ROM capacity 32K bytes (CXP84332M) 40K bytes (CXP84340M) * Incorporated RAM capacity 1120 bytes * Peripheral functions -- A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 16s/20MHz) -- Serial interface 8-bit, 8-stage FIFO incorporated (Auto transfer for 1 to 8 bytes), 1 channel 8-bit clock synchronization, 1 channel -- Timers 8-bit timer 8-bit timer/counter 19-bit time base timer 16-bit capture timer/counter 32kHz timer/counter -- Remote control reception circuit 8-bit pulse measuring counter, 6-stage FIFO -- PWM output 14 bits, 1 channel * Interruption 15 factors, 15 vectors, multi-interruption possible * Standby mode SLEEP/STOP * Package 80-pin plastic QFP * Piggyback/evaluation chip CXP84300 80-pin ceramic QFP Structure Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E95X06-ST
Block Diagram
AVss
AVREF
NMI
INT0 INT1 INT2 INT3
TEX TX EXTAL XTAL RST VDD Vss
AN0 to AN7 SPC700 CPU CORE CLOCK GENERATOR/ SYSTEM CONTROL 7
8 8
A/D CONVERTER
PA0 to PA7
PB0 to PB6 PB7 8 PC0 to PC7
PWM
14 BIT PWM GENERATOR
RMC FIFO ROM 32K/40K BYTES RAM 1120 BYTES
REMOCON
CS0 SI0 SO0 SCK0 FIFO
INTERRUPT CONTROLLER
8 4 2
PD0 to PD7 PE0 to PE3 PE4 to PE5 PF0 to PF7
SERIAL INTERFACE UNIT 0
TO CINT EC1 ADJ 2 2
PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A
PRESCALER/ TIME BASE TIMER 32kHz TIMER/COUNTER 8
-2-
2
SI1 SO1 SCK1
SERIAL INTERFACE UNIT 1
8
PG0 to PG7
EC0
8 BIT TIMER/COUNTER 0
8 BIT TIMER 1
8
PH0 to PH7
16 BIT CAPTURE TIMER/COUNTER2
8
PI0 to PI7 CXP84332M/84340M
CXP84332M/84340M
Pin Assignment (Top View)
PF2
PF1
PF0
PG7
PG6
PG5
PG4
VDD
PG3
PG2
PG1
PG0
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PF3 PF4 PF5 PF6 PF7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0 PH1 PH2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PI4 PI3/INT3 PI2/INT2 PI1/INT1 PI0/INT0 PE5/TO/ADJ PE4/PWM PE3/NMI PE2/RMC PE1/EC1 PE0/EC0 PB7/SO1 PB6/SI1 PB5/SCK1 PB4/SO0 PB3/SI0 PB2/SCK0 PB1/CS0 PB0/CINT PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3
NC
PI7
PI6 PA1/AN1
Note) NC (Pin 73) must be connected to VDD.
-3-
PA0/AN0
PA2/AN2
EXTAL
AVREF
XTAL
AVSS
RST
PH3
PH4
PH5
PH6
PH7
TEX
VSS
TX
PI5
CXP84332M/84340M
Pin Description Pin code I/O (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of the pull-up resistance can be set through the software in a unit of 4 bits. (8 pins) (Port B) Lower 7-bit I/O port in which I/O can be set in a unit of single bits. Also, an uppermost bit (PB7) exclusively for output. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Functions
PA0/AN0 to PA7/AN7
I/O/Analog input
Analog inputs to A/D converter. (8 pins)
PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1
I/O/Input I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input Output/Output
External capture input to 16-bit timer/counter. Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1).
PC0 to PC7
I/O
(Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving 12mA sync current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) External event inputs for timer/counter. (2 pins) (Port E) 6-bit port. Lower 4 bits are for inputs; upper 2 bits are for outputs. (6 pins) Remote control reception circuit input. Non-maskable interruption request input. 14-bit PWM output. Rectangular wave output for 16-bit timer/counter and output for 32kHz oscillation frequency demultiplication. (Port F) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins)
PD0 to PD7
I/O
PE0/EC0 PE1/EC1 PE2/RMC PE3/NMI PE4/PWM PE5/TO/ADJ
Input/Input Input/Input Input/Input Input/Input Output/Output Output/Output/ Output
PF0 to PF7
I/O
-4-
CXP84332M/84340M
Pin code
I/O
Functions (Port G) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) (Port H) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) (Port I) 8-bit I/O ports. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) External interruption request inputs. (4 pins)
PG0 to PG7
I/O
PH0 to PH7
I/O
PI0/INT0 to PI3/INT3 PI4 to PI7 EXTAL XTAL TEX TX RST NC AVREF AVss VDD Vss
I/O/Input I/O Input Output Input Output Input
Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Crystal connectors for 32kHz timer/counter clock oscillaton circuit. For usage as event counter, input to TEX, and open TX. Low-level active, system reset. NC. Under normal operating conditions, connect to VDD.
Input
Reference voltage input for A/D converter. A/D converter GND. Vcc supply. GND
-5-
CXP84332M/84340M
I/O Circuit Format for Pins Pin Port A
Pull-up resistance "0" when reset Port A data
Circuit format
When reset
PA0/AN0 to PA7/AN7
Data bus
Port A direction "0" when reset
IP
Input protection circuit
Hi-Z
RD (Port A) Port A input selection "0" when reset A/D converter Input multiplexer Pull-up transistors approx. 10k
8 pins Port B
Pull-up resistance "0" when reset Port B data
PB0/CINT PB1/CS0 PB3/SI0 PB6/SI1
Data bus
Port B direction "0" when reset Schmitt input RD (Port B) CINT CS0 SI0 SI1
IP
Hi-Z
4 pins Port B
Pull-up resistance "0" when reset SCK OUT Output enable Port B output selection "0" when reset Port B data Port B direction "0" when reset Data bus RD (Port B)
Pull-up transistors approx. 10k
PB2/SCK0 PB5/SCK1
IP
Hi-Z
Schmitt input
2 pins
SCK in
Pull-up transistors approx. 10k
-6-
CXP84332M/84340M
Pin Port B
Pull-up resistance "0" when reset SO Output enable Port B output selection
Circuit format
When reset
PB4/SO0
"0" when reset Port B data Port B direction "0" when reset Data bus RD (Port B) IP
Hi-Z
1 pin Port B
SO Output enable Port B output selection "1" when reset Port B data
Pull-up transistors approx. 10k
Internal reset signal
PB7/SO1
()
2 1
High level with approx. 200k resistor when reset
Data bus
1 pin Port C
RD (Port B)
Pull-up transistors approx. 200k
Pull-up resistance "0" when reset Port C data
PC0 to PC7
Port C direction "0" when reset Data bus RD (Port C) 1 Large current 12mA 2 Pull-up transistors approx. 10k IP
Hi-Z
8 pins Port E PE0/EC0 PE1/EC1 PE2/RMC PE3/NMI 4 pins
Schmitt input IP
EC0 EC1 RMC/NMI Data bus RD (Port E)
Hi-Z
-7-
CXP84332M/84340M
Pin Port E
Circuit format
PWM Port E output selection "0" when reset Port E data "1" when reset Data bus
When reset
PE4/PWM
High level
1 pin Port E
RD (Port E)
PE5/TO/ADJ
Output enable TO ADJ16K ADJ2K Port E output selection Port E output selection "00" when reset Port E output selection "0" when reset Port E data "1" when reset Data bus
MPX
High level
ADJ signals are frequency dividing outputs for 32kHz oscillation frequency adjustment ADJ2K provides usage as buzzer output.
1 pin Port D Port F Port G Port H PD0 to PD7 PF0 to PF7 PG0 to PG7 PH0 to PH7 PI4 to PI7 Port I
RD (Port E)
Pull-up resistance "0" when reset Ports D, F, G, H, I data
Ports D, F, G, H, I directon "0" when reset Data bus RD (Ports D, F, G, H, I)
IP
Hi-Z
Pull-up transistors approx. 10k
36 pins
-8-
CXP84332M/84340M
Pin Port I
Circuit format
Pull-up resistance "0" when reset Port I data
When reset
PI0/INT0 to PI3/INT3
Data bus
Port I direction "0" when reset Schmitt input RD (Port I)
IP
Hi-Z
4 pins
INT0 INT1 INT2 INT3
Pull-up transistors approx. 10k
EXTAL XTAL
EXTAL
IP
IP
* Diagram shows circuit composition during oscillation. * Feedback resistor is removed during stop.
Oscillation
2 pins
XTAL
TEX TX
TEX
IP
IP
* Diagram shows circuit composition during oscillation.
Oscillation
* When the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed, and TEX and TX become "Low" level and "High" level respectively.
2 pins
TX
Pull-up resistance
RST
Mask option OP IP Schmitt input
Low level
1 pin
-9-
CXP84332M/84340M
Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage High level output current Symbol VDD AVSS VIN VOUT IOH Ratings -0.3 to +7.0 -0.3 to +0.3 -0.3 to +7.01 -0.3 to +7.01 -5 -50 15 20 100 -20 to +75 -55 to +150 600 Unit V V V V mA mA mA mA mA C C mW Output per pin Total for all output pins
(Vss = 0V reference) Remarks
High level total output current IOH Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation IOL IOLC IOL Topr Tstg PD
Value per pin, excluding large current outputs Value per pin2 for large current outputs Total for all output pins
1) VIN and VOUT must not exceed VDD + 0.3V. 2) The large current drive transistor is the N-ch transistor of Port C (PC). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI.
Recommended Operating Conditions Item Symbol Min. 4.5 Supply voltage VDD 3.5 2.7 2.5 VIH High level input voltage VIHS VIHEX VIL Low level input voltage Operating temperature VILS VILEX Topr 0.7VDD 0.8VDD Max. 5.5 5.5 5.5 5.5 VDD VDD V V V V V V C V Unit
(Vss = 0V reference) Remarks Guaranteed operation range for high speed mode1 Guaranteed operation range for low speed mode1 Guaranteed operation range with TEX clock Guaranteed data hold range during STOP 2 Hysteresis input3 EXTAL4 2 Hysteresis input3 EXTAL4
VDD - 0.4 VDD + 0.3 0 0 -0.3 -20 0.3VDD 0.2VDD 0.4 +75
1) High speed mode is 1/2 frequency dividing clock selection; low-speed mode is 1/16 frequency dividing clock selection. 2) Value for each pin of normal input ports (PA, PB3, PB4, PB6, PC, PD, PF to PH, PI4 to PI7). 3) Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0, EC1, RMC, NMI, INT0, INT1, INT2, INT3. 4) Specifies only during external clock input. - 10 -
CXP84332M/84340M
Electrical Characteristics DC Characteristics Item High level output current Low level output current Symbol VOH PA to PD, PE4, PE5, PF to PI VOL PC IIHE IILE IIHT Input current IILT IILR IIL I/O leakage current IIZ TEX RST1 PA to PD2, PF to PI2 EXTAL Pins Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 4.5V, VIL = 4.0V 0.5 -0.5 0.1 -0.1 -1.5 (Ta = -20 to +75C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 40 -40 10 -10 -400 -2.0 -10 10 Typ. Max. Unit V V V V V A A A A A mA A A
PE0 to PE3, VDD = 5.5V, VI = 0, 5.5V RST1 High-speed mode operation (1/2 frequency dividing clock) VDD = 5.5V, 20MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) VDD SLEEP mode VDD = 5.5V, 20MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) STOP mode 1.4
IDD1
32
52
mA
IDD2 Power supply current3
38
100
A
IDDS1
10
mA
IDDS2
9
30
A
IDDS3
VDD = 5.5V, termination of 20MHz and 32kHz crystal oscillation PA, PB0 to PB6, PC, PD, Clock 1MHz PE0 to PE3, 0V for all pins excluding measured PF to PI, pins EXTAL, XTAL, TEX, TX, RST
10
A
Input capacity
CIN
10
20
pF
1) RST specifies the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. 2) PA to PD, and PF to PI pins specifie the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. (Excludes output PB7) 3) When all pins are open. - 11 -
CXP84332M/84340M
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time System clock frequency Event count input clock input pulse width Event count input clock rise time, fall time 1) Symbol fC Pin
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Min. 1 23.0 200 Typ. Max. 20 Unit MHz ns ns ns 20 ms
XTAL Fig. 1, Fig. 2 EXTAL EXTAL EXTAL EC0 EC1 EC0 EC1 TEX TX TEX TEX Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3
tXL, tXH tCR, tCF tEH, tEL tER, tEF
fC
tsys + 501
32.768
kHz
tTL, tTH tTR, tTF
10 20
s ms
tsys indicates the three values below according to the upper two bits (CPU clock selected) of the control
clock register (address: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Fig. 1. Clock timing
1/fc
VDD - 0.4V EXTAL 0.4V
tXH
tCF
tXL
tCR
Fig. 2. Clock applied conditions
Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition Crystal oscillation
EXTAL
XTAL
EXTAL
XTAL
TEX
TX
C1
C2
74HC04
C1
C2
Fig. 3. Event count clock timing
TEX EC0 EC1
0.8VDD 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR
- 12 -
CXP84332M/84340M
(2) Serial transfer (CH0) Item CS0 SCK0 delay time CS0 SCK0 float delay time CS0 SO0 delay time CS0 SO0 float delay time CS0 High level width SCK0 cycle time SCK0 High, Low level width SI0 input set-up time (for SCK0 ) SI0 input hold time (for SCK0 ) SCK0 SO0 delay time Note 1) Symbol Pin SCK0
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss reference) Condition Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tDCSK
tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200
2tsys + 200 16000/fc
tDCSKF SCK0 tDCSO
SO0
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
SCK0
SCK0
tsys + 100
8000/fc - 50 100 200
SI0
SI0
tsys + 200
100
SO0
tsys+200
100
ns ns
tsys indicates the three values below according to the upper two bits (CPU clock selected) of the
control clock register (address: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
- 13 -
CXP84332M/84340M
Fig. 4. Serial transfer CH0 timing
tWHCS
CS0
0.8VDD
0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Output data 0.2VDD
- 14 -
CXP84332M/84340M
Serial transfer (CH1) Item SCK1 cycle time Symbol Pin SCK1
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 1000 16000/fc 400 8000/fc - 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
SCK1 High, Low level width SI1 input set-up time (for SCK1 ) SI1 input hold time (for SCK1 ) SCK1 SO1 delay time
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer CH1 timing
tKCY tKL tKH
SCK1 0.8VDD 0.2VDD
tSIK
tKSI
0.8VDD SI1 Input data 0.2VDD
tKSO
0.8VDD SO1 0.2VDD Output data
- 15 -
CXP84332M/84340M
(3) A/D converter characteristics (Ta = -20 to +75C, VDD = 4.5 to 5.5V, AVREF = 4.0 to VDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time VZT1 VFT2 Ta = 25C VDD = AVREF = 5.0V VSS = AVSS = 0V -10 4870 160/fADC3 12/fADC3 AVREF AN0 to AN7 Operation mode AVREF IREFS SLEEP mode STOP mode 32kHz operation mode VDD - 0.5 0 0.6 VDD AVREF 1.0 10 10 4970 Symbol Pin Condition Min. Typ. Max. 8 5 110 5070 Unit Bits LSB mV mV s s V V mA A
tCONV tSAMP
VIAN IREF
Reference input voltage VREF Analog input voltage
AVREF current
Fig. 6. Definition of A/D converter terms
FFH FEH
Digital conversion value
1) VZT : Value at which the digital transfer value changes from 00H to 01H and vice versa. 2) VFT : Value at which the digital transfer value changes from FEH to FFH and vice versa. 3) fADC indicates the values below due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F9H) and bits 7 (PCK1) and 6 (PCK0) of the clock control register (CLC: 00FEH).
VFT Analog input
Linearity error 01H 00H VZT
CKS PCK1, 0 00 ( = fEX/2) 01 ( = fEX/4) 11 ( = fEX/16)
0 (/2 selection) fADC = fC/2 fADC = fC/4 fADC = fC/16
1 ( selection) fADC = fC fADC = fC/2 fADC = fC/8
- 16 -
CXP84332M/84340M
(4) Interruption, reset input Item
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin INT0 INT1 INT2 INT3 NMI RST Condition Min. Max. Unit
External interruption High, Low level width
tIH tIL tRSL
1
s
Reset input Low level width
32/fc
s
Fig 7. Interruption input timing
tIH tIL
0.8VDD INT0 INT1 INT2 INT3 NMI (NMI specifies only for the falling edge.) 0.2VDD tIL tIH
Fig. 8. RST input timing
tRSL
RST 0.2VDD
- 17 -
CXP84332M/84340M
Appendix Fig. 9. Recommended oscillation circuit
(i) Main clock
(ii) Main clock
(iii) Sub clock
EXTAL
XTAL Rd
EXTAL
XTAL Rd
EXTAL TEX
XTAL TX Rd
C1
C2
C1
C2
Products List Manufacturer MURATA MFG CO., LTD. Model CSA16.00MXZ072 CSA20.00MXZ046 RIVER ELETEC CO., LTD. KINSEKI LTD. HC-49/U03 P3 fc (MHz) 16.00 20.00 16.00 20.00 32.768kHz C1 (pF) C2 (pF) Rd () Circuit example (i)
0 8 6 50
0 8 6 22
0
0 1M
(ii) (iii)
Mask option table Item Reset pin pull-up resistance Content Non-existent Existent
- 18 -
CXP84332M/84340M
Example of Representative Characteristics
IDD vs. VDD
(fc = 20MHz, Ta = 25C, Typical) 50 30 20 10 1/16 dividing mode 5 SLEEP mode 1/2 dividing mode 1/4 dividing mode 30
IDD vs. fc
(VDD = 5V, Ta = 25C, Typical)
1/2 dividing mode
IDD - Supply current [mA]
IDD - Supply curren [mA]
1 0.5 (500A)
20 1/4 dividing mode
32kHz mode (instruction)
0.1 (100A) 1.05 (50A) 0.01 (10A) 0 1 2 3 4 5 6 7 32kHz SLEEP mode
10
1/16 dividing mode SLEEP mode 0 5 10 Frequency [MHz] 15 20
VDD - Supply voltage [V]
- 19 -
CXP84332M/84340M
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 64 41 + 0.1 0.15 - 0.05 0.15
65
40
+ 0.4 14.0 - 0.1
17.9 0.4
A 80 25 + 0.2 0.1 - 0.05
0.8 0.2 M
+ 0.15 0.35 - 0.1
+ 0.35 2.75 - 0.15
0 to 10 DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.6g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
SONY CODE EIAJ CODE JEDEC CODE
QFP-80P-L01 QFP080-P-1420
- 20 -
0.8 0.2
1
24
16.3

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