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Motorola
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| Part No. |
MC100ES6210
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| OCR Text |
...s SiGe technology supports near-zero output skew Supports DC to 3GHz operation of clock or data signals ECL/PECL compatible differential clo...Delay CLKA to QAx or CLKB to QBx Differential output voltage (peak-to-peak) fO < 1.1 GHz fO < 2.5 GH... |
| Description |
Low Voltage 2.5/3.3V Dlfferentlal ECL/PECL/HSTL fanout Buffer
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| File Size |
112.29K /
8 Page |
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it Online |
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Motorola
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| Part No. |
MC100ES6254
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| OCR Text |
...
SiGe technology supports near-zero output skew Supports DC to 3GHz operation1 of clock or data signals LVPECL compatible differential cloc...delay CLK, 1 to QA[] or QB[] Output-to-output skew Output-to-output skew Output pulse skewe Output d... |
| Description |
2.5/3.3V Dlfferentlal LVPECL 2x2 Clock Clock Swltch and fanout Buffer
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| File Size |
128.77K /
12 Page |
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it Online |
Download Datasheet |
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Motorola
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| Part No. |
MPC9952
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| OCR Text |
...for the use of the device as a "zero delay" buffer. Any of the eleven outputs can be used as the feedback to the PLL. The VCO_Sel pin allows for the choice of two VCO ranges to optimize PLL stability and jitter performance. The MR/OE pin al... |
| Description |
Low Voltage PLL Clock Drlver
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| File Size |
103.09K /
8 Page |
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it Online |
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Xilinx Inc
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| Part No. |
XC5202-3PC84C
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| OCR Text |
...performance and reduces noise - Zero Flip-Flop hold time for input registers simplifies system timing - Independent Output Enables for exter...delay element to control input set-up time. This element can be used to avoid potential hold-time pr... |
| Description |
FPGA,64-CELL,CMOS,LDCC,84PIN,PLASTIC
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| File Size |
516.09K /
73 Page |
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it Online |
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Fairchild
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| Part No. |
MM74HC423A
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| OCR Text |
...ent through resistor REXT to be zero. Both comparators are "OFF" with the total device current due only to reverse junction leakages. An add...delay from trigger to Q is independent of the value of CEXT, REXT, or the duty cycle of the input wa... |
| Description |
Dual Retriggerable Monostable Multivibrator
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| File Size |
128.52K /
10 Page |
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it Online |
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Motorola
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| Part No. |
MPC9351
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| OCR Text |
...uts * External feedback enables zero-delay configurations * Output enable/disable and static test mode (PLL enable/disable) * Low skew characteristics: maximum 150 ps output-to-output * Cycle-to-cycle jitter max. 22 ps RMS * 32 lead LQFP pa... |
| Description |
Low Voltage PLL Clock Drlver
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| File Size |
170.73K /
12 Page |
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it Online |
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Motorola
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| Part No. |
MPC9773
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| OCR Text |
... External PLL feedback supports zero-delay capability * Various feedback and output dividers (see application section) * Supports up to three individual generated output clock frequencies * Synchronous output clock stop circuitry for each i... |
| Description |
3.3V 1:12 LVCMOS PLL Clock Generator
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| File Size |
216.68K /
20 Page |
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it Online |
Download Datasheet |
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Motorola
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| Part No. |
MPC930
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| OCR Text |
...has been optimized for use as a zero delay buffer. In addition to tighter specification limits on the phase offset of the device, a higher speed VCO has been used on the MPC931. The MPC930, on the other hand, is more optimized for use as a ... |
| Description |
Low Voltage PLL Clock Drlver
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| File Size |
158.51K /
14 Page |
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it Online |
Download Datasheet |
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Price and Availability
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