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Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
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| Part No. |
CY7C1474V33-200BGI CY7C1472V33-250BZXI CY7C1470V33-200AXCT
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| OCR Text |
...250-mhz device) ? clock enable (cen ) pin to suspend operation ? synchronous self-timed writes ? cy7c1470v33, cy7c1472v33 available in jede...u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register ... |
| Description |
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBLArchitecture 1M X 72 ZBT SRAM, 3 ns, PBGA209
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBLArchitecture 4M X 18 ZBT SRAM, 3 ns, PBGA165
2M X 36 ZBT SRAM, 3 ns, PQFP100
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| File Size |
498.88K /
29 Page |
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Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
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| Part No. |
CY7C1371D-100AXI CY7C1371D-100BGI CY7C1373D-100BZI CY7C1373D-133AXI CY7C1371D-100BZC CY7C1371D-100BZI CY7C1373D-100AXC CY7C1373D-100AXI CY7C1371D-100AXC CY7C1373D-133AXC CY7C1371D-133AXI CY7C1373D-100BZC CY7C1371D-133BGC CY7C1371D-133BGI CY7C1371D-133AXC CY7C1373D-100BGC CY7C1373D-133BGC CY7C1373D-133BGXI CY7C1373D-133BZXC CY7C1373D-133BZXI CY7C1373D-133BZI CY7C1373D-133BGXC CY7C1373D-133BZC CY7C1371D-133BGXC CY7C1371D-100BGXI ICY7C1373D-100BGXI CY7C1373D-100BZXC CY7C1371D-100BZXC CY7C1371D-100BGC ICY7C1373D-100BGI
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| OCR Text |
...100-mhz device) ? clock enable (cen ) pin to enable clock and suspend operation ? synchronous self-timed writes ? asynchronous output enabl...u t p u t b u f f e r s e zz sleep control logic block diagram ? cy7c1371d (512k x 36) c mode bw a b... |
| Description |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 8.5 ns, PQFP100
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 18兆位（为512k × 36/1M × 18）流体系结构，通过与NoBLTM的SRAM
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 8.5 ns, PBGA165
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 6.5 ns, PBGA119
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 512K X 36 ZBT SRAM, 8.5 ns, PBGA165
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 6.5 ns, PQFP100
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 6.5 ns, PBGA165
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 512K X 36 ZBT SRAM, 8.5 ns, PBGA119
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| File Size |
449.66K /
30 Page |
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Freescale (Motorola)
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| Part No. |
MC33290
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| OCR Text |
... d x scir x d scit x d mcu v dd cen r x t x v bb iso gnd 5.0 nf(3) 27 v(3) 1.0 nf 5.0 v 10 nf(3) 500 ? (2) d(1) 45 v(2) +v bat +v dd iso k...u c t o r , i ... |
| Description |
ISO9141 Serial Link Interface
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| File Size |
395.26K /
12 Page |
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1474V25-250BGXI CY7C1472V25-167BZXI CY7C1474V25-167BGI
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| OCR Text |
...250-mhz device) ? clock enable (cen ) pin to suspend operation ? synchronous self-timed writes ? cy7c1470v25, cy7c1472v25 available in jede...u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register ... |
| Description |
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBLArchitecture 1M X 72 ZBT SRAM, 3 ns, PBGA209
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBLArchitecture 4M X 18 ZBT SRAM, 3.4 ns, PBGA165
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBLArchitecture 1M X 72 ZBT SRAM, 3.4 ns, PBGA209
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| File Size |
496.26K /
28 Page |
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Integrated Device Technology, Inc.
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| Part No. |
IDT71T75902
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| OCR Text |
...write signal input synchronous cen clock enable input synchronous bw 1 , bw 2 , bw 3 , bw 4 individual byte write sele cts input synchro...u u u u u 512k x 36, 1m x 18 memory configurations u u u u u supports high performance system speed ... |
| Description |
512K x 36, 1M x 18 2.5V Synchronous ZBTSRAMs 2.5V I/O, Burst Counter Flow-Through Outputs 12k × 3600万18⑩为2.5V同步ZBT SRAM.5VI / O的突发反流，通过输出
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| File Size |
638.87K /
26 Page |
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1474BV33-200BGC
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| OCR Text |
... 250 mhz device) clock enable (cen ) pin to suspend operation synchronous self timed writes cy7c1470bv33, cy7c1472bv33 available in jede...u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register ... |
| Description |
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V 1M X 72 ZBT SRAM, 3 ns, PBGA209
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| File Size |
814.29K /
31 Page |
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AZM[Arizona Microtek, Inc]
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| Part No. |
AZ10E131FN AZ100E131 AZ100E131FN AZ10E131
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| OCR Text |
...LOW and using the Clock Enable (CEn) inputs for clocking. Common clocking is achieved by holding the CEn inputs LOW and using CC to clock a...U V W X T Z G1 K1
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 ... |
| Description |
ECL/PECL 4-bit D Flip-Flop
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| File Size |
72.15K /
6 Page |
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