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  zero-delay fanout Datasheet PDF File

For zero-delay fanout Found Datasheets File :: 485    Search Time::4.781ms    
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    CY23FP12-002 CY3692 CY23FP12OC-002 CY23FP12OC-002T CY23FP12OI-002 CY23FP12OI-002T

Cypress Semiconductor, Corp.
Part No. CY23FP12-002 CY3692 CY23FP12OC-002 CY23FP12OC-002T CY23FP12OI-002 CY23FP12OI-002T
OCR Text Zero Delay Buffer Features * Pre-programmed Configurations * Fully field-programmable -- Input and output dividers -- Inverting/noninverting outputs -- Phase-locked loop (PLL) or fanout buffer configuration 10-MHz to 200-MHz operating ran...
Description 23FP SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 5.30 MM, SSOP-28
200-MHz Field Programmable Zero Delay Buffer

File Size 207.98K  /  10 Page

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    MPC951

Motorola, Inc
Part No. MPC951
OCR Text ... for the MPC951 to be used as a zero delay, low skew fanout buffer. In addition, the external feedback allows for a wider variety of input-to-output frequency relationships. The MPC951 REF_SEL pin allows for the selection of an alternate LV...
Description LOW VOLTAGE PLL CLOCK DRIVER

File Size 109.33K  /  13 Page

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    CYPRESS[Cypress Semiconductor]
Part No. CY23FP12 CY23FP12OXC CY23FP12OXCT CY23FP12OXI CY23FP12OXIT CY3692 CY23FP12OC CY23FP12OCT CY23FP12OI CY23FP12OIT CY3672
OCR Text Zero Delay Buffer Features * Fully field-programmable -- Input and output dividers -- Inverting/noninverting outputs -- Phase-locked loop (PLL) or fanout buffer configuration * 10-MHz to 200-MHz operating range * Split 2.5V or 3.3V output...
Description 200-MHz Field Programmable Zero Delay Buffer

File Size 199.21K  /  10 Page

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    PCS2I9942P PCS2I9942PG-32-ER PCS2I9942PG-32-ET PCS2I9942PG-32-LR PCS2I9942PG-32-LT PCS2P9942PG-32-ER PCS2P9942PG-32-ET P

Alliance Semiconductor, Corp.
PulseCore Semiconductor
Part No. PCS2I9942P PCS2I9942PG-32-ER PCS2I9942PG-32-ET PCS2I9942PG-32-LR PCS2I9942PG-32-LT PCS2P9942PG-32-ER PCS2P9942PG-32-ET PCS2P9942PG-32-LR PCS2P9942PG-32-LT
OCR Text ...e board trace, therefore, CL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel terminat...Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = R...
Description 9942 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 7 X 7 MM, 0.80 MM HEIGHT, GREEN, TQFP-32
9942 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 7 X 7 MM, 0.80 MM HEIGHT, GREEN, LQFP-32
Low Voltage 1:18 Clock Distribution Chip

File Size 429.33K  /  10 Page

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    Motorola
Part No. MPC958
OCR Text ...e the MPC958 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will tristate the output buffers when driven "high". The MPC958 is fully...
Description Low Voltage PLL Clock Drlver
From old datasheet system

File Size 103.78K  /  8 Page

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    Fairchild Semiconductor Corporation
Part No. AN-90
OCR Text ...cause the propagation delay for zero load capacitance is not zero and depends on the internal structure of each device, an offset term must be added that is unique to a particular device type. Since each data sheet gives propagation delay f...
Description 74C Family Characteristics

File Size 210.47K  /  7 Page

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    Motorola
Part No. MPC954
OCR Text ...is a 3.3V compatible, PLL based zero delay buffer targeted for high performance clock tree designs. With 11 outputs at frequencies of up to 100MHz and output skews of 200ps the MPC954 is ideal for the most demanding clock tree designs. The ...
Description Low Voltage PLL Clock Drlver
From old datasheet system

File Size 89.34K  /  8 Page

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    PCK953BD PCK953

NXP Semiconductors
PHILIPS[Philips Semiconductors]
Part No. PCK953BD PCK953
OCR Text ...e the PCK953 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will reset the internal counters and 3-State the output buffers when dri...
Description 50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver

File Size 65.55K  /  8 Page

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    Motorola
Part No. MPC954
OCR Text ...is a 3.3v compatible, pll based zero delay buffer targeted for high performance clock tree designs. with 11 outputs at frequencies of up to 100mhz and output skews of 200ps the mpc954 is ideal for the most demanding clock tree designs. the ...
Description LOW VOLTAGE PLL CLOCK DRIVER

File Size 100.32K  /  8 Page

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    MPC958

Motorola Inc
MOTOROLA[Motorola, Inc]
Part No. MPC958
OCR Text ...e the MPC958 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will tristate the output buffers when driven "high". The MPC958 is fully...
Description LOW VOLTAGE PLL CLOCK DRIVER

File Size 252.60K  /  8 Page

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For zero-delay fanout Found Datasheets File :: 485    Search Time::4.781ms    
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