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Integrated Circuit Syst...
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| Part No. |
ICS1892Y-14LF ICS1892
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| OCR Text |
....................... 13 chapter 4 overview of the ics 1892 .................................................................... 15 4.1 100ba...pair interface ................................................................................ 30 6... |
| Description |
10Base-T/100Base-TX Integrated PHYceiver
1 CHANNEL(S), SERIAL COMM CONTROLLER, PQFP64
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| File Size |
803.42K /
148 Page |
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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
9ERS3165BKILF
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| OCR Text |
...3 62 ref/fslc/test_sel pci2/tme 4 61 vddref pci3 5 60 x1 pci4/27_sel 6 59 x2 pci5_f/itp_en 7 58 gndref gndpci 8 57 fslb/test_mode vdd48 9 56...pair the power-up default is pci0 output, but this pin may also be used as a clock request control ... |
| Description |
400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64
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| File Size |
321.47K /
26 Page |
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PROMOS TECHNOLOGIES INC
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| Part No. |
V59C1512404QCF-25
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| OCR Text |
4 banks x 32mbit x 4 (404) 4 banks x 16mbit x 8 (804) 4 banks x 8mbit x 16 (164) v59c1512(404/804/164)qc rev.1.2 june 2008 5 37 3 25a 25 19...pair of bidirectional strobes (dqs, dqs ) in a source synchronous fashion. operating the four memory... |
| Description |
DDR DRAM, PBGA60
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| File Size |
1,240.83K /
78 Page |
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it Online |
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CYPRESS SEMICONDUCTOR CORP
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| Part No. |
MT57W1MH18BF-5 MT57W1MH18BF-3.3
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| OCR Text |
...s (300 mhz) -3.3 4ns (250 mhz) -4 5ns (200 mhz) -5 6ns (167 mhz) -6 7.5ns (133 mhz) -7.5 configurations 2 meg x 8 mt57w2mh8b 1 meg x 18 mt...pair by tying c and c# high. in this mode, the sram will use k and k# in place of c and c#. this mod... |
| Description |
1M X 18 DDR SRAM, 0.45 ns, PBGA165
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| File Size |
372.38K /
27 Page |
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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
MC100ES6535DTR2 MC100ES6535EJ
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| OCR Text |
4 june 9, 2009 1 ?2009 integrated device technology, inc. 3.3v lvcmos-to-lvpecl 1:4 fanout buffer mc100es6535 the mc100es6535 is a low sk...pair 14, 15 q2, q2 output lvpecl differential output pair 16, 17 q1, q1 output lvpecl differential o... |
| Description |
100E SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
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| File Size |
642.97K /
8 Page |
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ANALOG DEVICES INC
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| Part No. |
AD9517-1ABCPZ
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| OCR Text |
....65 ghz external vco/vcxo to 2.4 ghz optional 1 differential or 2 single-ended reference inputs reference monitoring capability automati...pair shares a 1-to-32 divider with coarse phase delay additive output jitter: 225 fs rms channel-... |
| Description |
9517 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC48
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| File Size |
1,082.37K /
80 Page |
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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
85304AG-01T
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| OCR Text |
...lk1 nclk1 pullup pulldown 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 q4 nq3 q3 nq2 q2 nq1 q1 nq0 q0 nq4 v cc clk_en v cc nclk1 clk1 ...pair. lvpecl interface levels. 3, 4 q1, nq1 output differential output pair. lvpecl interface lev... |
| Description |
85304 SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
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| File Size |
675.30K /
15 Page |
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AVAGO TECHNOLOGIES LIMI...
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| Part No. |
HEDS-5500I11 HEDM-5505B04 HEDS-5500F02 HEDM-5500
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| OCR Text |
... output of channel b. there are 4 states per cycle, each nominally 90e. state width error ( ?s): the deviation, in electrical degrees, of each state width from its ideal value of 90e. phase (): the number of electrical degrees be... |
| Description |
Quick Assembly Two and Three Channel Optical Encoders
SINGLE, 2 CHANNELS, ROTARY OPTICAL POSITION ENCODER
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| File Size |
1,546.75K /
12 Page |
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