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![NB4N527S](Maker_logo/on_semiconductor.GIF)
ON Semiconductor
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Part No. |
NB4N527S
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OCR Text |
...ting anylevel tm input signal (lvpecl, cml, hstl, lvds, or lvttl/lvcmos) to lvds. depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signa... |
Description |
Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer, with Internal Termination
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File Size |
167.06K /
10 Page |
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it Online |
Download Datasheet
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Integrated Device Techn...
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Part No. |
IDT8T49N222I
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OCR Text |
...s, individually programmable as lvpecl or lvds ? outputs may be individually set to use 2.5v or 3.3v output levels ? individually programmable outp ut frequencies: 7.29mhz up to 1200mhz ? two differential inputs support the following inp... |
Description |
Fourth generation FemtoClock
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File Size |
697.58K /
40 Page |
View
it Online |
Download Datasheet
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Integrated Device Techn...
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Part No. |
IDT8T49N205I
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OCR Text |
...net option requiring a 125mhz lvpecl clock translated from the same 19.44mhz input reference. to implement other configurations , these power-up default settings can be overwritten after power-up using the i 2 c interface and the devic... |
Description |
Fourth Generation FemtoClock
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File Size |
732.27K /
41 Page |
View
it Online |
Download Datasheet
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Price and Availability
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