...der
Mode Register
Address buffer & Refresh Counter
Bank0
Amplifier
Command Decoder
/RAS /CAS /WE
Control Logic
/CS
...clock /CAS Latency = 3 Cycle time /CAS Latency = 2 Symbol Min tCK3 tCK2 tCHW tCLW tAC3 tAC2 tRC tRRC...
Description
Synchronous DRAM(4M X 8 Bit X 4 Banks) Synchronous DRAM(4M X 8 Bit X 4 Banks) 同步DRAM4米8位4银行 Synchronous DRAM(4M X 8 Bit X 4 Banks) 同步DRAM米8位4银行 133 Mhz LVTTL synchronous DRAM, 4 M x 8 bit x 4 banks