lvcmos pdf Datasheet P15 Full Text Search --- IC-ON-LINE


	Part Number	Hot Search : 1SS35 19371251 24PVXI AS7805A CZRT5237 SRP300J CPC1965Y YB1521
	Product Description
	Full Text Search

lvcmos Datasheet PDF File

For lvcmos Found Datasheets File :: 9359 Search Time::0.969ms
Page :: | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | <15> |

				Integrated Device Technology
Part No.	8N4QV01
OCR Text	...he power-up default frequency ? lvcmos/lvttl compatible control inputs ? rms phase jitter @ 156.25mhz (12khz - 20mhz): 0.494ps (typical) ? rms phase jitter @ 156.25mhz (1khz - 40mhz): 0.594ps (typical) ? 2.5v or 3.3v supply voltage mode...
Description	IDT8N4QV01
File Size	158.28K / 20 Page	View it Online	Download Datasheet

				Motorola, Inc. MOTOROLA[Motorola, Inc]
Part No.	MPC9140
OCR Text	lvcmos Fanout Buffer The MPC9140 is a 1:18 lvcmos fanout buffer targeted to support Intel based Pentium IITM microprocessor chip sets. The device features 18 low skew outputs optimized to drive the clock inputs of standard unbuffered SDRAM...
Description	80000 SYSTEM GATE 1.5 VOLT FPGA 1:18 lvcmos FANOUT BUFFER
File Size	102.23K / 6 Page	View it Online	Download Datasheet

				Rectron Semiconductor
Part No.	NBSG86ABAHTBG
OCR Text	...tive ecl), pecl (positive ecl), lvcmos/lvttl, cml, or lvds. the output level select (ols) input is used to program the peak ? to ? peak output amplitude between 0 and 800 mv in five discrete steps. the nbsg86a employs input default circuitr...
Description
File Size	191.30K / 14 Page	View it Online	Download Datasheet

				Alliance Semiconductor ... ALSC[Alliance Semiconductor Corporation]
Part No.	ASM4SSTVF32852 ASM4SSTVF32852-114BT ASM4ISSTVF32852-114BR ASM4ISSTVF32852-114BT ASM4SSTVF32852-114BR
OCR Text	...STL_2 I/O levels except for the lvcmos RESETB input. Data flow from D to Q is controlled by the differential clock (CLK/CLKB) and a control signal (RESETB). The positive edge of CLK is used to trigger the data flow, and CLKB is used to main...
Description	DDR 24-Bit to 48-Bit Registered Buffer SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA114 Specialty Clock Management 2.3 V -2.7 V, DDR 24-bit to 48-bit registered buffer
File Size	106.12K / 13 Page	View it Online	Download Datasheet

				Diodes, Inc. Integrated Circuit Systems ICS
Part No.	ICSSSTVF16859BK ICSSSTVF16859BG ICSSSTVF16859 ICSSSTVF16859YK
OCR Text	...TL_2 I/O levels, except for the lvcmos RESET# input. Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge of CLK is used to trigger the data flow and CLK# is used to maint...
Description	DDR 13-Bit to 26-Bit Registered Buffer 复员13位至26位注册缓冲区 13:26 Register
File Size	184.80K / 10 Page	View it Online	Download Datasheet

For lvcmos Found Datasheets File :: 9359 Search Time::0.969ms
Page :: | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | <15> |