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  zero-delay fanout Datasheet PDF File

For zero-delay fanout Found Datasheets File :: 485    Search Time::4.64ms    
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    MPC9331

Motorola, Inc
Part No. MPC9331
OCR Text ... external PLL feedback Supports zero-delay operation in external feedback mode PLL multiplies the reference clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3 or x/4 Synchronous output clock stop in logic low eliminates output runt pulses ...
Description 3.3 V 1:6 LVCMOS PLL CLOCK GENERATOR

File Size 305.14K  /  12 Page

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    MPC9352

Motorola, Inc
Part No. MPC9352
OCR Text ...6/2003 3.3V/2.5V 1:11 LVCMOS Zero Delay Clock Generator The MPC9352 is a 3.3V or 2.5V compatible, 1:11 PLL based clock generator targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output ske...
Description 3.3V / 2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR

File Size 377.32K  /  16 Page

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    MPC93R51D MPC93R51

Motorola, Inc
Part No. MPC93R51D MPC93R51
OCR Text ...uts * External feedback enables zero-delay configurations * Output enable/disable and static test mode (PLL enable/disable) * Low skew characteristics: maximum 150 ps output-to-output * Cycle-to-cycle jitter max. 22 ps RMS * 32 lead LQFP pa...
Description LOW VOLTAGE PLL CLOCK DRIVER

File Size 293.44K  /  12 Page

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    IDT5V9910A IDT5V9910A-2SO IDT5V9910A-5SOI IDT5V9910A-7SOI IDT5V9910A-2SOI IDT5V9910A-5SO IDT5V9910A-7SO IDT5V9910A-7SOGI

Integrated Device Technology, Inc.
IDT[Integrated Device Technology]
Part No. IDT5V9910A IDT5V9910A-2SO IDT5V9910A-5SOI IDT5V9910A-7SOI IDT5V9910A-2SOI IDT5V9910A-5SO IDT5V9910A-7SO IDT5V9910A-7SOGI IDT5V9910A-5SOGI IDT5V9910A-5SOGI8 IDT5V9910A-5SOI8
OCR Text .... FEATURES: * * * * * * Eight zero delay outputs <250ps of output to output skew Selectable positive or negative edge synchronization Synchronous output enable Output frequency: 15MHz to 85MHz 3 skew grades: IDT5V9910A-2: tSKEW0<250ps IDT...
Description 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK? JR.
3.3V Low Skew PLL Clock Driver TurboClock Jr.

File Size 88.18K  /  6 Page

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    IDT5V991A-2JG IDT5V991A-2JI IDT5V991A-5J IDT5V991A-5JI IDT5V991A-7JI IDT5V991A IDT5V991A-2J IDT5V991A-2JGI IDT5V991A-5JG

Integrated Device Technology, Inc.
IDT[Integrated Device Technology]
Part No. IDT5V991A-2JG IDT5V991A-2JI IDT5V991A-5J IDT5V991A-5JI IDT5V991A-7JI IDT5V991A IDT5V991A-2J IDT5V991A-2JGI IDT5V991A-5JG IDT5V991A-5JGI IDT5V991A-7J IDT5V991A-7JG IDT5V991A-7JGI
OCR Text ...l pins can be left open for the zero skew default setting. The Control Summary Table shows how to select specific skew taps by using the nF1...Delay(1,9) Output Duty Cycle Variation from 50%(1) Output HIGH Time Deviation from 50%(1,10) Output ...
Description 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32
Scan Test Devices With 18-Bit Inverting Bus Transceivers 56-SSOP -40 to 85
Scan Test Devices With 20-Bit Universal Bus Transceivers 64-LQFP -40 to 85
From old datasheet system

File Size 74.99K  /  8 Page

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    MPC9772

Motorola, Inc
Part No. MPC9772
OCR Text ... External PLL feedback supports zero-delay capability Various feedback and output dividers (see application section) Supports up to three individual generated output clock frequencies Synchronous output clock stop circuitry for each individ...
Description 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR

File Size 235.31K  /  16 Page

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    Motorola, Inc.
Part No. MPC9447 MPC9447D
OCR Text ...of the input signal with a near zero skew. The outputs buffers support driving of 50 terminated transmission lines on the incident edge: eac...Delay Output Disable Time Output Enable Time Setup Time Hold Time Output-to-Output Skew Device-to-De...
Description 3.3V/2.5V 1:9 LVCMOS CLOCK fanout BUFFER

File Size 229.78K  /  12 Page

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    SY55852U SY55852UKCTR SY55852UKG SY55852UKC SY55852UKGTR SY55852UKI SY55852UKITR 55852U

MICREL[Micrel Semiconductor]
Part No. SY55852U SY55852UKCTR SY55852UKG SY55852UKC SY55852UKGTR SY55852UKI SY55852UKITR 55852U
OCR Text ...flop into a known state, namely zero. Power Supply. TRUTH TABLE D X X X 0 1 CLK X 0 1 R 1 0 0 0 0 Q 0 QN-1 QN-1 0 1 /Q 1 /QN-1 /QN-1 1 0...Delay Set-Up Time Hold Time Reset Recovery Minimum Pulse Width CLK to Q R to Q tr,tf Note 1. Con...
Description D FLIP-FLOP

File Size 50.71K  /  7 Page

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For zero-delay fanout Found Datasheets File :: 485    Search Time::4.64ms    
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