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LATTICE[Lattice Semiconductor] Lattice Semiconductor Corporation Lattice Semiconductor, Corp.
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Part No. |
ISPLSI2032VE ISPLSI2032VE-110LB49 ISPLSI2032VE-110LJ44 ISPLSI2032VE-110LT44 ISPLSI2032VE-110LT48 ISPLSI2032VE-135LB49 ISPLSI2032VE-135LJ44 ISPLSI2032VE-135LT44 ISPLSI2032VE-135LT48 ISPLSI2032VE-180LB49 ISPLSI2032VE-180LJ44 ISPLSI2032VE-180LT44 ISPLSI2032VE-180LT48 ISPLSI2032VE-225LB49 ISPLSI2032VE-225LJ44 ISPLSI2032VE-225LT44 ISPLSI2032VE-225LT48 2032VE ISPLSI2032VE-225LB44
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OCR Text |
...lock Frequency, Max. Toggle GLB reg. Setup Time before Clock, 4 PT Bypass GLB reg. Clock to Output Delay, ORP Bypass GLB reg. Hold Time after Clock, 4 PT Bypass GLB reg. Setup Time before Clock
154 250 2.5 - 0.0 3.5 - 0.0 - 3.5 - - - - 2... |
Description |
225 MHz 3.3V in-system prommable superFAST high density PLD 3.3V In-System Programmable High Density SuperFAST?/a> PLD 3.3V In-System Programmable High Density SuperFAST?/a> PLD 3.3V In-System Programmable High Density SuperFAST⑩ PLD 3.3V In-System Programmable High Density SuperFAST PLD IC,Normally-Open Panel-Mount Solid-State Relay,1-CHANNEL,M:HL048HD4.4 IC,Normally-Open Panel-Mount Solid-State Relay,1-CHANNEL,M:HL048HD4.3 IC,Normally-Closed Panel-Mount Solid-State Relay,1-CHANNEL,M:HL048HD4.4 EE PLD, 13 ns, PQCC44 3.3V In-System Programmable High Density SuperFASTPLD EE PLD, 13 ns, PQFP44 3.3V In-System Programmable High Density SuperFASTPLD EE PLD, 6 ns, PQCC44 3.3V In-System Programmable High Density SuperFASTPLD 3.3在系统可编程高密度PLD的超快⑩ 3.3VIn-SystemProgrammableHighDensitySuperFASTPLD
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File Size |
174.87K /
14 Page |
View
it Online |
Download Datasheet |
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LATTICE[Lattice Semiconductor] Lattice Semiconductor Corporation Lattice Semiconductor, Corp.
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Part No. |
ISPLSI2032VL ISPLSI2032VL-110LB49 ISPLSI2032VL-110LJ44 ISPLSI2032VL-110LT44 ISPLSI2032VL-110LT48 ISPLSI2032VL-135LB49 ISPLSI2032VL-135LJ44 ISPLSI2032VL-135LT44 ISPLSI2032VL-135LT48 ISPLSI2032VL-180LB49 ISPLSI2032VL-180LJ44 ISPLSI2032VL-180LT44 ISPLSI2032VL-180LT48 2032VL ISPLSI2032VL-135LT44I
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OCR Text |
...lock Frequency, Max. Toggle GLB reg. Setup Time before Clock, 4 PT Bypass GLB reg. Clock to Output Delay, ORP Bypass GLB reg. Hold Time after Clock, 4 PT Bypass GLB reg. Setup Time before Clock Clock Frequency with External Feedback ( tsu2 ... |
Description |
2.5VIn-SystemProgrammableSuperFASTHighDensityPLD 2.5V In-System Programmable SuperFAST⑩ High Density PLD 2.5V In-System Programmable SuperFAST High Density PLD 2.5V In-System Programmable SuperFASTHigh Density PLD EE PLD, 10 ns, PQFP48 2.5V In-System Programmable SuperFASTHigh Density PLD EE PLD, 10 ns, PQFP44 2.5V In-System Programmable SuperFASTHigh Density PLD EE PLD, 7.5 ns, PQFP44 2.5V In-System Programmable SuperFASTHigh Density PLD EE PLD, 5 ns, PQCC44 2.5V In-System Programmable SuperFASTHigh Density PLD EE PLD, 5 ns, PQFP44
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File Size |
152.73K /
12 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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