...gnal VRAM read signal VRAM chip enable Dot data output bus to X driver Dot data shift clock for X driver Chip enable shift clock for X drive...disable time VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V min max min max 10 -- 10 -- 0 -- 0 -- See note -- S...
...s
tPZH/PZL
3-state output enable time OE to Qn 3-state outpiut disable time OE to Qn LE pulse width HIGH
VI = Vcc or GND
ns
tPHZ/PLZ
VI = Vcc or GND
ns
tW
ns
tsu
Setup time Dn to LE
ns
th
Hold time ...
...de: temperature sense or master enable input, 2.5V and 5V reference outputs for expanding monitor functions, two Pin-Detect enable inputs fo...disable/enable
VDD Pin Detect PD1#
ENPG
FAULT# UV
SMH4811A
OV
PG#
DC/DC
Pin De...
... 25 26 27 28 29 30 31 32 output enable output amplifier balanced output output amplifier balanced output converter analog ground 2 I balance...disable isolation maximum gain 1 dB compression point 2nd order harmonic of 5 to 65 MHz signal 3rd o...